5 k

5 k

5 k

0.1 µF

Via to Power/Ground Plane

Via to Internal Plane

Internal Layer Trace

Top/Bottom Layer Trace

I

2C Bus

MCU INT

WCSP Ball

ALERT

V+

A0

SDA

GND

SCL

TMP108

Top View

19

TMP108

www.ti.com

SBOS663A – APRIL 2013 – REVISED SEPTEMBER 2019

Product Folder Links: TMP108

Submit Documentation Feedback

Copyright © 2013–2019, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended

value of this bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate for

noisy or high-impedance power supplies. Pull up the open-drain output pins (SDA , SCL and ALERT) through 5-

kΩ pullup resistors.

10.2 Layout Example

Figure 18. TMP108 Layout