TMP106 datasheet(10/20 Pages) TI2

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TMP106

SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006

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TIMING DIAGRAMS

The TMP106 is Two-Wire- and SMBus-compatible.

Figure 4 to Figure 7 describe the various operations on the

TMP106. Bus definitions are given below. Parameters for

Figure 4 are defined in Table 12.

Bus Idle: Both SDA and SCL lines remain HIGH.

Start Data Transfer: A change in the state of the SDA line,

from HIGH to LOW, while the SCL line is HIGH, defines a

START condition. Each data transfer is initiated with a

START condition.

Stop Data Transfer: A change in the state of the SDA line

from LOW to HIGH while the SCL line is HIGH defines a

STOP condition. Each data transfer is terminated with a

repeated START or STOP condition.

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not limited and

is determined by the master device. The receiver

acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed,

is obliged to generate an Acknowledge bit. A device that

acknowledges must pull down the SDA line during the

Acknowledge clock pulse in such a way that the SDA line

is stable LOW during the HIGH period of the Acknowledge

clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data

transfer can be signaled by the master generating a

Not-Acknowledge on the last byte that has been

transmitted by the slave.

PARAMETER

FAST MODE

HIGH-SPEED MODE

UNITS

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL Operating Frequency

f(SCL)

0.001

0.4

0.001

3.4

MHz

Bus Free Time Between STOP and START Condition

t(BUF)

600

160

Hold time after repeated START condition.

After this period, the first clock is generated.

t(HDSTA)

100

Repeated START Condition Setup Time

t(SUSTA)

100

STOP Condition Setup Time

t(SUSTO)

100

Data Hold Time

t(HDDAT)

Data Setup Time

t(SUDAT)

100

SCL Clock LOW Period

t(LOW)

1300

160

SCL Clock HIGH Period

t(HIGH)

600

Clock/Data Fall Time

300

160

Clock/Data Rise Time

300

160

for SCLK

≤ 100kHz

1000

Table 12. Timing Diagram Definitions for the TMP106

TWO-WIRE TIMING DIAGRAMS

SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(BU F )

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

Figure 4. Two-Wire Timing Diagram

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