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M65KG256AB датащи(PDF) 23 Page - STMicroelectronics

номер детали M65KG256AB
подробное описание детали  256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM
PDF  51 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M65KG256AB датащи(HTML) 23 Page - STMicroelectronics

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M65KG256AB
5 Registers description
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5
Registers description
The DDR Mobile RAM has the two mode registers, the Mode Register and the Extended Mode
register.
5.1
Mode Register description
The Mode Register is used to select the CAS Latency, Burst Type, and Burst Length of the
device:
The CAS Latency defines the number of clock cycles after which the first data will be
output during a Burst Read operation.
The Burst Type specifies the order in which the burst data will be addressed. This order is
programmable either to sequential or interleaved (see Table 5: Burst Type Definition).
The Burst Length is the number of Words that will be output or input during a Burst Read
or Write operation. It can be configured as 2, 4, 8 or 16 Words.
The Mode Register must be programmed at the end of the Power-Up sequence prior to issuing
any command. It is loaded by issuing a Mode Register Set command (MRS), with BA0-BA1 are
set to ‘00’ to select the Mode Register.
Table 7: Mode Register Definition, shows the available Mode Register configurations.
Table 7.
Mode Register Definition
Address
Bits
Mode
Register Bit
Register Description
Value
Description
A12-A7
-
-
000000
A6-A4
MR6-MR4
CAS Latency Bits
(Read Operations)
011
3 Clock Cycles
Other configurations reserved
A3
MR3
Burst Type Bit
0
Sequential
1
Interleaved
A2-A0
MR2-MR0
Burst Length Bit
001
2 Words
010
4 Words
011
8 Words
100
16 Words
Other configurations reserved
BA1-BA0
-
-
00



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