M65KG256AB datasheet(21/51 Pages) STMICROELECTRONICS

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M65KG256AB

4 Operating modes

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Read is completed. tRPST from the last falling edge of the data strobe, the DQS pins become

High-Z. This low period of DQS is referred as Read Postamble.

See Table 5: Burst Type Definition, Table 15: AC Characteristics, Table 16: AC Characteristics

Measured in Clock Period, and Figures 9 and 11, for a detailed description of Burst Read

operation and characteristics.

Burst Read can be terminated by issuing a Burst Read Terminate command (see Section 3.6:

Burst Read Terminate command (BST) and Figure 12: Burst Terminate During Read

Operation).

The interval between Burst Read to Burst Read and Burst Read to Burst Write commands are

described in Figures 7, 8 and 20.

4.3

Burst Write

The M65KG256AB is switched in Burst Write mode by issuing a Bank (Row) Activate command

to set the bank and column addresses to be written to, followed by a Write command (see

sections 3.3: Bank(Row) Activate command (ACT) and 3.7: Write command (WRIT) for details).

Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the A10

Address Input. If A10 is High (set to ‘1’) when the Write command is issued, the Write operation

will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), Auto Precharge is not

selected and the row will remain active for subsequent accesses.

Burst Write operations can be performed either at Byte or at Word level. The CAS Latency for

Burst Write operations is fixed to 1 clock cycle.

UDQS/LDQS input act as the strobe for the input data and UDQM/LDQM select the Byte to be

written. UDQS/LDQS must be Low tWPRE prior to their first rising edge; and can be changed to

High-Z tWPST after their last falling edge. These two periods of time are referred to as Write

Preamble and Write Postamble, respectively.

See Table 15: AC Characteristics, Table 16: AC Characteristics Measured in Clock Period, and

Figures 15, 17, and 18, for a detailed description of Burst Write AC waveforms and

characteristics.

The interval between Burst Write to Burst Write commands are described in Figures 13, 14, 21

and 22.

4.4

Self Refresh

In the Self Refresh mode, the data contained in the DDR LPSDRAM memory array is retained

and refreshed. The size of the memory array to be refreshed is programmed in the Extended

Mode Register. Only the data contained in the part of the array selected for Self Refresh will be

retained and refreshed. In this respect, this is a power saving feature.

The Self Refresh mode is entered and exited by issuing a Self Refresh Entry and Self Refresh

Exit command, respectively (see Section 3: Commands). When in this mode, the device is not

clocked any more.

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