CLK

C

C

PRE

D

CLR

C

C

C

C

C

C

C

C

Q

Q

9

SN74HCS72-Q1

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SCLS774 – OCTOBER 2019

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Copyright © 2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

Figure 10 describes the SN74HCS72-Q1. As the SN74HCS72-Q1 is a dual D-Type negative-edge-triggered flip-

flop with clear and preset, the diagram below describes one of the two device flip-flops.

8.2 Functional Block Diagram

Figure 10. Logic Diagram (Positive Logic) for one channel of SN74HCS72-Q1

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The drive capability of this device may

create fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. It is important for the output power of the device to be limited to avoid damage due to over-

current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all

times.

8.3.2 CMOS Schmitt-Trigger Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the

Electrical Characteristics, using ohm's law (R = V ÷ I).

The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,

which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower

than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly

will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger

inputs, please see Understanding Schmitt Triggers.