PCA8574ATS datasheet(15/27 Pages) NXP

15 / 27 page

PCA8574_PCA8574A_2

Product data sheet

Rev. 02 — 14 May 2007

15 of 27

NXP Semiconductors

PCA8574/74A

Remote 8-bit I/O expander for I2C-bus with interrupt

13. Dynamic characteristics

[1]

tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2]

tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

[4]

The maximum tf for the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage tf is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed tf.

[5]

Cb = total capacitance of one bus line in pF.

[6]

Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Table 8.

Dynamic characteristics

VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = −40 °Cto+85 °C; unless otherwise speciﬁed. Limits are for Fast-mode I2C-bus.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCL

SCL clock frequency

400

kHz

tBUF

bus free time between a STOP and START

condition

1.3

µs

tHD;STA

hold time (repeated) START condition

0.6

µs

tSU;STA

set-up time for a repeated START condition

0.6

µs

tSU;STO

set-up time for STOP condition

0.6

µs

tHD;DAT

data hold time

tVD;ACK

data valid acknowledge time[1]

0.1

0.9

µs

tVD;DAT

data valid time[2]

tSU;DAT

data set-up time

100

tLOW

LOW period of the SCL clock

1.3

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

fall time of both SDA and SCL signals

[3][4] 20 + 0.1Cb[5] -

300

rise time of both SDA and SCL signals

20 + 0.1Cb[5] -

300

tSP

pulse width of spikes that must be suppressed

by the input ﬁlter[6]

Port timing; CL ≤ 100 pF (see Figure 8 and Figure 9)

tv(Q)

data output valid time

µs

tsu(D)

data input set-up time

µs

th(D)

data input hold time

µs

Interrupt timing; CL ≤ 100 pF (see Figure 8 and Figure 9)

tv(D)

data input valid time

µs

td(rst)

reset delay time

µs

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