PCA8574_PCA8574A_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 14 May 2007

6 of 27

NXP Semiconductors

PCA8574/74A

7.

Functional description

Refer to Figure 1 “Block diagram of PCA8574/74A”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of

8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on

AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in

Table 4 “PCA8574 address map” and Table 5 “PCA8574A address map”.

Remark: When using the PCA8574A, the General Call address (0000 0000b) and the

Device ID address (1111 100Xb) are reserved and cannot be used as device address.

Failure to follow this requirement will cause the PCA8574A not to acknowledge.

The last bit of the first byte defines the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation.

PCF8574A is applied.

7.1.1 Address maps

Fig 7.

PCA8574/74A address

R/W

002aab636

A6

A5

A4

A3

A2

A1

A0

programmable

slave address

Table 4.

PCA8574 address map

A6

A5

A4

A3

A2

A1

A0

Address

010000020h

010000121h

010001022h

010001123h

010010024h

010010125h

010011026h

010011127h