PL133-21 datasheet(4/14 Pages) MICROCHIP

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PL133-21

DS20006309B-page 4



2020 Microchip Technology Inc.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1

Layout Recommendations

The following guidelines are to assist you with a

performance-optimized PCB design.

3.1.1

SIGNAL INTEGRITY AND

TERMINATION CONSIDERATIONS

• Keep traces short.

• Trace = Inductor. With a capacitive load this

equals ringing.

• Long trace = Transmission Line. Without proper

termination this will cause reflections (looks like

ringing).

• Design long traces as “striplines” or “microstrips”

with defined impedance.

• Match trace at one side to avoid reflections

bouncing back and forth.

3.1.2

DECOUPLING AND POWER

SUPPLY CONSIDERATIONS

• Place decoupling capacitors as close as possible

to the VDD pin to limit noise from the power

supply.

• Multiple VDD pins should be decoupled

separately for best performance.

• The addition of a ferrite bead in series with VDD

can help prevent noise from other board sources.

• The value of decoupling capacitor is frequency

dependent. Typical values to use are 0.1 µF for

designs using crystals <50 MHz and 0.01 µF for

designs using crystals >50 MHz.

FIGURE 3-1:

Typical CMOS Termination.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Pin Type

Description

FIN

Reference clock input.

CLK1

Clock output (inverted).

GND

Ground connection.

CLK0

Clock output (inverted).

VDD

VDD connection.

Output enable input.

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