AM53C94JC datasheet(32/63 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53C94/Am53C96

CNTLREG3 – Bit 0 – BS8 – Burst Size 8

The BS8 bit is used to modify the timing of the DREQ

signal with respect to the

DMARD and DMAWR signals.

The BS8 bit is used in conjunction with the Modify DMA

Mode (MDM) bit in the CNTLREG3. Both bits have to be

set for proper operation.

When the BS8 bit is set the device delays the assertion

of the DREQ signal until 8 bytes or 4 words transfer is

possible.

When the BS8 bit is set and the device is in a DMA write

mode the DREQ signal will be asserted only when 8 byte

locations are available for writing. In the DMA read

mode the DREQ signal will go active under the following

circumstances:

At the end of a transfer,

In the target mode,

– when the transfer is complete

– when the

ATN signal is active

In the initiator mode,

– when the Current Transfer Register

is decremented to zero

– after any phase change

In the middle of a transfer

In the initiator mode,

– when the last 8 bytes of the FIFO are full

– during Synchronous Data-In transfer when the

Event Transfer Count Register is greater than

7 and the last 8 bytes of the FIFO are full.

When the BS8 bit is reset and the device is in a DMA

read or write mode the DREQ signal will toggle every

time the data is strobed by the

DMARD or DMAWR

signals.

Using Bit 0 (BS8) and Bit 1 (MDM) of Control

modes shown in the table below.

Maximum

(MDM) (BS8)

Function

Synchronous

Bit 1

Bit 0

Offset

Normal DMA Mode

Burst Size 8 Mode

Reserved

–

Modified DMA Mode

Data Alignment Register (0FH) Write

16506C-33

The Data Alignment Register (DALREG) is used if the

first byte of a 16-bit DMA transfer from the SCSI bus to

the host processor is misaligned. Prior to issuing an in-

formation transfer command, the host processor must

set the Data Alignment Enable (DAE) bit in the

CNTLREG2.

DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0

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