AM53C94JC datasheet(29/63 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53C94/Am53C96

Clock Factor Register (09H) Write

Clock Factor Register

CLKFREG

Address: 09H

Type: Write

7654

210

RES

CLKF2

CLKF1

CLKF0

xxxxx

Reserved

Clock Factor 2:0

Reserved

16506C-29

The Clock Factor Register (CLKFREG) must be set to

indicate the input frequency range of the device. This

value is crucial for controlling various timings to meet the

SCSI specification. The selector can be calculated by

rounding off the quotient of (Input Clock Frequency in

MHz)/(5 MHz). The device has a frequency range of 10

to 25 MHz.

CLKFREG – Bits 7:3 – RES – Reserved

CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0

The CLKF 2:0 bits specify the binary coded value of the

clock factor. The CLKF 2:0 bits will default to a value of 2

by a hard or soft reset.

Input Clock

CLKF2

CLKF1

CLKF0

Frequency in MHz

10.01 to 15

15.01 to 20

20.01 to 25

Forced Test Mode Register (0AH) Write

Forced Test Mode Register

FTMREG

Address: 0AH

Type: Write

7654

210

RES

FHI

FIM

FTM

xxxxx

Reserved

Forced High Impedance Mode

Forced Initiator Mode

Forced Target Mode

Reserved

16506C-30

The Forced Test Mode Register (FTMREG) is for test

use only. The STE bit in the CNTLREG1 must be set for

the FTMREG to operate.

FTMREG – Bits 7:3 – RES – Reserved

FTMREG – Bit 2 – FHI – Forced High Impedance

Mode

The FHI bit when set places all the output and bidirec-

tional pins into a high impedance state.

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