AM53C94JC datasheet(31/63 Pages) AMD

31 / 63 page

P R E L I M I N A R Y

AMD

Am53C94/Am53C96

Group 2 Command Recognition: When the S2FE bit is

set the group 2 commands are recognized as 10 byte

commands. The GCV (Group Code Valid) bit in the

STATREG (04H) is set. When the S2FE bit is reset, the

device will interpret the group 2 commands as reserved

commands and will request 6 byte commands. The

GCV bit in the STATREG will not be set in this case.

CNTLREG2 – Bit 2 – ACDPE – Abort on Command/

Data Parity Error

The ACDPE bit when set allows the device to abort a

command or data transfer when a parity error is de-

tected. When the ACDPE bit is reset parity error is ig-

nored.

CNTLREG2 – Bit 1 – PGRP – Pass Through/Gener-

ate Register Parity

The PGRP bit when set causes the data along with the

parity from the host to pass through to the FIFO under

the control of the

CS and the WR signals. When the

PGRP bit is reset, the device generates the parity on the

data from the host before writing it to the FIFO.

When the device is placing the data on the SCSI bus, it

will check for an outgoing parity error if either the PGRP

bit is set or the PGDP (Pass Through/Generate Data

Parity) bit is set.

CNTLREG2 – Bit 0 – PGDP – Pass Through/Gener-

ate Data Parity

The PGDP bit when set causes the data along with the

parity from the host to pass through to the FIFO under

the control of the

DACK and the WR signals. When the

PGDP bit is reset, the device generates the parity on the

data from the host before writing it to the FIFO.

When the device is placing the data on the SCSI bus, it

will check for an outgoing parity error if either the PGDP

bit is set or the PGRP (Pass Through/Generate Register

Parity) bit is set.

Control Register Three

CNTLREG3

Address: 0CH

Type: Read/Write

765

210

RES

LBTM

MDM

BS8

00000

000

Reserved

Last Byte Transfer Mode

Modify DMA Mode

Burst Size 8

Reserved

16506C-32

Control Register Three (0CH) Read/Write

CNTLREG3 – Bits 7:3 – RES – Reserved

CNTLREG3 – Bit 2 – LBTM – Last Byte Transfer

Mode

The LBTM bit specifies how the last byte in an odd byte

transfer is handled during 16-bit DMA transfers. This

mode is not used if byte control is selected via BUSMD

1:0 inputs and BSO (Byte Select Order) bit in the

CNTLREG2. This mode has no affect during 8-bit DMA

transfers and on transfers on the SCSI bus.

When the LBTM bit is set the DREQ signal will not be

asserted for the last byte, instead the host will read or

write the last byte from or to the FIFO. When the LBTM

bit is reset the DREQ signal will be asserted for the last

byte and the following 16-bit DMA transfer will contain

the last byte on the lower bus. If the transfer is a DMA

read the upper bus will be all ones.

The LBTM bit is reset by hard or soft reset.

CNTLREG3 – Bit 1 – MDM – Modify DMA Mode

The MDM bit is used to modify the timing of the

DACK

signal with respect to the

DMARD and DMAWR signals.

The MDM bit is used in conjunction with the Burst Size 8

(BS8) bit in the CNTLREG3. Both bits have to be set for

proper operation.

When the MDM bit is set and the device is in a DMA read

or write mode the

DACK signal will remain asserted

while the data is strobed by the

DMARD or DMAWR sig-

nals. In the DMA read mode when BUSMD 1:0 = 11 the

DACK signal will toggle for every DMA read.

When the MDM bit is reset and the device is in a DMA

read or write mode the

DACK signal will toggle every

time the data is strobed by the

DMARD or DMAWR

signals.

AM53C94JC датащи(PDF) 31 Page - Advanced Micro Devices

AM53C94JC датащи(HTML) 31 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

датащи скачать

ссылки URL