PLL1705

PLL1706

SLES046A − AUGUST 2002 − REVISED SEPTEMBER 2002

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12

Program-Register Bit Mapping

The built-in functions of the PLL1706 are controlled through a 16-bit program register. This register is loaded using MD,

MC and ML. After the 16 data bits are clocked in using the rising edge of MC, ML is used to latch the data into the register.

Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in

Figure 12 and Figure 13, respectively.

ML

MC

MD

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 12. Serial Mode Control Format

t(MLL)

VDD/2

MC

MD

MSB

ML

t(MHH)

VDD/2

VDD/2

t(MLS)

t(MLH)

t(MCL)

t(MCH)

LSB

t(MDH)

t(MCY)

t(MDS)

t(MLS)

DESCRIPTION

SYMBOL

MIN

TYP

MAX

UNIT

MC pulse cycle time

tMCY

100

ns

MC pulse duration LOW

tMCL

40

ns

MC pulse duration HIGH

tMCH

40

ns

MD hold time

tMDH

40

ns

MD setup time

tMDS

40

ns

ML low-level time

tMLL

16

MC clocks(1)

ML high-level time

tMHH

200

ns

ML hold time(2)

tMLH

40

ns

ML setup time(3)

tMLS

40

ns

(1) MC clocks: MC clock period

(2) MC rising edge for LSB to ML rising edge

(3) ML rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any ML rise time is accepted.

Figure 13. Control Data Input Timing