PCM3000ESLASH2K datasheet(25/44 Pages) TI2

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T0019-03

Reset

Internal Reset

DAC VOUT

32/fS

Reset Removal or Power Down(1) Off

ADC DOUT

Zero Data

Normal Data(2)

VCOM

(0.5 VCC2)

4096/fS

Zero Data

Ready/Operation

EXTERNAL RESET

t(RST)

Reset Removal

1024 System Clock Periods

RSTB

Internal Reset

System Clock

(XTI or CLKIO)

t(RST) = 40 ns (min)

Reset

T0015-04

RSTB Pulse Duration

SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM

PCM3000

PCM3001

SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004

(1)

Power down is for PCM3000 only.

(2)

The HPF transient response (exponentially attenuated signal from

±1.5% dc with 200-ms time constant) appears

initially.

Figure 26. DAC Output and ADC Output for Reset and Power Down

The PCM3000/3001 includes a reset input, RSTB (pin 28). As shown in Figure 27, the external reset signal must

drive RSTB low for a minimum of 40 nanoseconds while the system clock is active in order to initiate the reset

sequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion.

Figure 26 shows the state of the DAC and ADC outputs during and after the reset sequence.

Figure 27. External Forced-Reset Timing

The PCM3000/3001 operates with LRCIN synchronized to the system clock. The codec does not require any

specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN

and the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bit

clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the

DAC stops within 1/fS, and the analog output is forced to bipolar zero (VCC2/2) until the system clock is

resynchronized to LRCIN. Internal operation of the ADC also stops within 1/fS, and the digital output codes are

set to bipolar zero until resynchronization occurs. If LRCIN is synchronized within 5 or fewer bit clocks to the

system clock, operation remains normal.

Figure 28 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to

bipolar zero (<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions

between normal data and undefined states, the output has discontinuities, which cause output noise.

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