поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

PCM3000E/2K датащи(PDF) 24 Page - Texas Instruments

номер детали PCM3000E/2K
подробное описание детали  18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

PCM3000E/2K датащи(HTML) 24 Page - Texas Instruments

Back Button PCM3000E/2K Datasheet HTML 20Page - Texas Instruments PCM3000E/2K Datasheet HTML 21Page - Texas Instruments PCM3000E/2K Datasheet HTML 22Page - Texas Instruments PCM3000E/2K Datasheet HTML 23Page - Texas Instruments PCM3000E/2K Datasheet HTML 24Page - Texas Instruments PCM3000E/2K Datasheet HTML 25Page - Texas Instruments PCM3000E/2K Datasheet HTML 26Page - Texas Instruments PCM3000E/2K Datasheet HTML 27Page - Texas Instruments PCM3000E/2K Datasheet HTML 28Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 24 / 44 page
background image
www.ti.com
t(CLKIH)
XTI or CLKIO
1.4 V
3.2 V
t(CLKIL)
T0005-06
XTI
0.8 V
2.0 V
CLKIO
POWER-ON RESET
1024 System Clock Periods
Reset
Reset Removal
4.4 V
4.0 V
3.6 V
VDD
Internal Reset
System Clock
(XTI or CLKIO)
T0014-04
3 Clocks Minimum
PCM3000
PCM3001
SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (MHz)
256 fS
384 fS
512 fS
32
8.1920
12.2880
16.3840
44.1
11.2896
16.9344
22.5792
48
12.2880
18.4320
24.5760
System clock pulse duration, HIGH
t(CLKIH)
12 ns (min)
System clock pulse duration, LOW
t(CLKIL)
12 ns (min)
Figure 24. External System Clock Timing
The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI or
CLKIO) is active and VDD > 4 V. For the PCM3001, the system clock must complete a minimum of 3 complete
cycles prior to VDD > 4 V to ensure proper reset operation. The initialization sequence requires 1024 system
cycles for completion, as shown in Figure 25. Figure 26 shows the state of the DAC and ADC outputs during and
after the reset sequence.
Figure 25. Internal Power-On Reset Timing
24



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com