PCM1740ESLASH2K datasheet(9/26 Pages) TI2

9 / 26 page

PCM1740

SBAS128B

www.ti.com

The PLL can generate one of nine pre-programmed system

clock rates for either 256fS or 384fS output. The PLL output

and sampling frequencies are programmed using Control

and the corresponding PLL output clock rates. The reset

default condition for the PLL is fS = 44.1kHz with SCKO =

384fS, or 16.9344MHz.

RESET OPERATION

POWER-ON RESET

The PCM1740 includes power-on reset circuitry for start up

initialization. The initialization sequence starts when VDD

exceeds 2.2V (typical). The initialization sequence requires

1024 PLL output (or SCKO) clock cycles for completion.

During initialization, both VOUTL and VOUTR are forced to

VCC/ 2. Figure 6 shows the power-on reset timing, while

Table II shows the reset default settings for user-program-

mable functions. The user should not attempt to write

control registers via the I2C-Bus interface during the initial-

ization sequence.

EXTERNAL RESET

The PCM1740 includes an external reset input, RST (pin

10). This input may be used to force an initialization se-

quence. As shown in Figure 7, the RST pin must be held low

for a minimum of 20ns. The initialization sequence will then

start on the rising edge of RST. Initialization requires 1024

PLL output (or SCKO) clock cycles for completion. During

initialization, both VOUTL and VOUTR are forced to VCC/2.

Table II shows the reset default settings for user-program-

mable functions. The user should not attempt to write

control registers via the I2C-Bus interface during the initial-

ization sequence.

SAMPLING

INTERNAL SYSTEM

FREQUENCY (LRCK)

Clock - 256fS

Clock - 384fS

16kHz

Half

4.096MHz

6.144MHz

32kHz

Normal

8.192MHz

12.288MHz

64kHz

Double

16.384MHz

24.576MHz

22.05kHz

Half

5.6448MHz

8.4672MHz

44.1kHz

Normal

11.2896MHz

16.9344MHz

88.2kHz

Double

22.5792MHz

33.8688MHz

24kHz

Half

6.144MHz

9.216MHz

48kHz

Normal

12.288MHz

18.432MHz

96kHz

Double

24.576MHz

36.864MHz

TABLE I. PLL Sampling and System Clock Frequencies.

1024 System Clock Periods

Reset

Reset Removal

2.4V

2.2V

2.0V

CC /VDD

Internal Reset

System Clock

(SCKO)

1024 System Clock Periods

Reset

Reset Removal

System Clock

(SCKO)

Internal Reset

RST

RST ≥ 20ns

FIGURE 6. Power-On Reset Operation.

FIGURE 7. External Reset Operation.

At power-up, the PLL requires 30ms start up time for

stabilization. The PLL also exhibits a settling time of 20ms

in response to changes in sampling frequency selection.

The PLL output continues to operate during power-on or

external reset sequences, with the sampling frequency set to

fS = 44.1kHz and SCKO = 384fS.

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