PCM1740

14

SBAS128B

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SYS

Audio System Clock (or SCKO)

The SYS bit is used to select the system clock (or SCKO) frequency, either 256fS or 384fS.

SYS = 0

384fS (default)

SYS = 1

256fS

DSR0

Sampling Frequency Multiplier

DSR1

The DSR0 and DSR1 bits are used to select the multiplier used in conjunction with the SF0 and SF1 bits.

DSR1

DSR0

Multiplier

0

0

Normal, x1 (default)

0

1

Double, x2

1

0

Half, x 1/ 2

1

1

Reserved

SF0

Sampling Frequency Select

SF1

The SF0 and SF1 bits are used to select the sampling frequency group (32kHz, 44.1kHz, or 48kHz). Frequency

selection must be made with an interval time greater than 20

µs. The DSR0 and DSR1 bits, described previously,

are used to select the multiplier.

SF1

SF0

Sampling Frequency Group

0

0

44.1kHz Group ( 22.05kHz, 44.1kHz, or 88.2kHz) (default)

0

1

48 kHz Group (24kHz, 48kHz, or 96kHz)

1

0

32 kHz Group (16kHz, 32kHz, or 64kHz)

1

1

Reserved

LD

Attenuation Data Load Control

The LD bit is used to simultaneously set the Left and Right digital attenuation data. When LD is set to ‘1’, the

digital attenuation data given by Registers 0 and 1 are loaded for the Left and Right channels. When LD is set

to ‘0’, updates to Registers 0 and 1 are ignored, and the attenuation settings remain as previously programmed

until LD is set to ‘1’.

LD = 0

Disabled

LD = 1

Enabled: Left and Right Attenuation Data Updated Simultaneously

IZD

Infinite Zero Detect Mute

The IZD bit is used to enable/disable the infinite zero detect mute function. The PCM1740 includes infinite zero

detection logic that monitors the audio data at the DATA input (pin 18). If the audio data for both the Left and

Right channels are all zeros for 65,536 continuous BCK clock cycles, the zero flag will be activated and output

amplifier will be disconnected from the output of the delta-sigma modulator. The output amplifier input is

switched to the DC common-mode voltage. This forces VOUTL and VOUTR to VCC/2. The ZERO output flag (pin

16) is not affected by the setting of this bit.

IZD = 0

Disabled (default)

IZD = 1

Enabled

OPE

DAC Operation Control

The OPE bit is used to enable/disable the operation of the DACs. When enabled, the DAC outputs are connected

to the output amplifier for normal operation. When disabled, the output amplifier is disconnected from the DAC

output and switched to the DC common-mode voltage. This forces VOUTL and VOUTR to VCC/2.

OPE = 0

Enabled: Normal Operation(default)

OPE = 1

Disabled: Outputs forced to VCC/2

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Register 4

res

res

res

res

res

1

0

0

res

res

res

res

res

OPE

IZD

LD