PCM1602A

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SLES146A – AUGUST 2005 – REVISED OCTOBER 2010

ELECTRICAL CHARACTERISTICS

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, system clock = 384 fS (fS = 44.1 kHz), and 24-bit data, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

24

Bits

DATA FORMAT

Audio data interface formats

Standard, I2S, left-justified

Audio data bit length

16-, 18-, 20-, 24-bit, selectable

Audio data format

MSB-first, binary 2s complement

VOUT1, VOUT2

5

200

fS

Sampling frequency

kHz

VOUT3, VOUT4, VOUT5, VOUT6

5

100

128 fS, 192 fS, 256 fS,

System clock frequency

384 fS, 512 fS, 768 fS

DIGITAL INPUT/OUTPUT

Logic family

TTL-compatible

VIH

2

Input logic level

Vdc

VIL

0.8

IIH

(1)

VIN = VDD

10

IIL

(1)

VIN = 0 V

–10

Input logic current

mA

IIH

(2)

VIN = VDD

65

100

IIL

(2)

VIN = 0 V

–10

VOH

IOH = –4 mA

2.4

Output logic level

Vdc

VOL

IOL = 4 mA

1

DYNAMIC PERFORMANCE(3)(4)

VOUT = 0 dB, fS = 44.1 kHz

0.002%

0.007%

VOUT = 0 dB, fS = 96 kHz

0.004%

VOUT = 0 dB, fS = 192 kHz

0.005%

THD+N

Total harmonic distortion + noise

VOUT = –60 dB, fS = 44.1 kHz

0.7%

VOUT = –60 dB, fS = 96 kHz

0.9%

VOUT = –60 dB, fS = 192 kHz

1%

EIAJ, A-weighted, fS = 44.1 kHz

99

105

Dynamic range

A-weighted, fS = 96 kHz

103

dB

A-weighted, fS = 192 kHz

102

EIAJ, A-weighted, fS = 44.1 kHz

99

105

SNR

Signal-to-noise ratio

A-weighted, fS = 96 kHz

103

dB

A-weighted, fS = 192 kHz

102

fS = 44.1 kHz

96

103

Channel separation

fS = 96 kHz

101

dB

fS = 192 kHz

100

Level linearity error

VOUT = –90 dB

±0.5

dB

DC ACCURACY

Gain error

±1

±6

% of FSR

Gain mismatch, channel-to-channel

±1

±3

% of FSR

Bipolar zero error

VOUT = 0.5 VCC at bipolar zero

±30

±60

mV

(1)

Pins 38, 40, 41, 45–47 (SCKI, BCK, LRCK, DATA1, DATA2, DATA3)

(2)

Pins 34–37 (MDI, MC, ML, RST)

(3)

Analog performance specifications are tested using a System Two™ Cascade audio measurement system by Audio Precision™ in the

averaging mode. The load connected to the analog output is 5 k

Ω or larger, via capacitive loading.

(4)

Conditions in 192-kHz operation are: system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS

in register 12.

Copyright © 2005–2010, Texas Instruments Incorporated

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