M58LR128GT datasheet(33/84 Pages) STMICROELECTRONICS

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M58LR128GT, M58LR128GB

READ MODES

Read operations can be performed in two different

ways depending on the settings in the Configura-

tion Register. If the clock signal is ‘don’t care’ for

the data output, the read operation is asynchro-

nous; if the data output is synchronized with clock,

the read operation is synchronous.

The read mode and format of the data output are

determined by the Configuration Register. (See

Configuration Register section for details). All

banks support both asynchronous and synchro-

nous read operations.

Asynchronous Read Mode

In Asynchronous Read operations the clock signal

is ‘don’t care’. The device outputs the data corre-

sponding to the address latched, that is the mem-

ory

array,

Status

Common

Flash

Interface or Electronic Signature depending on the

command issued. CR15 in the Configuration Reg-

ister must be set to ‘1’ for asynchronous opera-

tions.

Asynchronous Read operations can be performed

in two different ways, Asynchronous Random Ac-

cess Read and Asynchronous Page Read. Only

Asynchronous Page Read takes full advantage of

the internal page storage so different timings are

applied.

In Asynchronous Read mode a Page of data is in-

ternally read and stored in a Page Buffer. The

Page has a size of 8 Words and is addressed by

address inputs A0, A1 and A2.

The first read operation within the Page has a

longer access time (tAVQV, Random access time),

subsequent reads within the same Page have

much shorter access times (tAVQV1, Page access

time). If the Page changes then the normal, longer

timings apply again.

The device features an Automatic Standby mode.

During Asynchronous Read operations, after a

bus inactivity of 150ns, the device automatically

switches to the Automatic Standby mode. In this

condition the power consumption is reduced to the

standby value and the outputs are still driven.

In Asynchronous Read mode, the WAIT signal is

always de-asserted.

See Table 23., Asynchronous Read AC Charac-

teristics, Figure 10., Asynchronous Random Ac-

cess

Read

Waveforms,

and

Figure

11., Asynchronous Page Read AC Waveforms, for

details.

Synchronous Burst Read Mode

In Synchronous Burst Read mode the data is out-

put in bursts synchronized with the clock. It is pos-

sible

perform

burst

reads

across

bank

boundaries.

Synchronous Burst Read mode can only be used

to read the memory array. For other read opera-

tions, such as Read Status Register, Read CFI

and Read Electronic Signature, Single Synchro-

nous Read or Asynchronous Random Access

Read must be used.

In Synchronous Burst Read mode the flow of the

data output depends on parameters that are con-

figured in the Configuration Register.

A burst sequence starts at the first clock edge (ris-

ing or falling depending on Valid Clock Edge bit

CR6 in the Configuration Register) after the falling

edge of Latch Enable or Chip Enable, whichever

occurs last. Addresses are internally incremented

and data is output on each data cycle after a delay

which depends on the X latency bits CR13-CR11

of the Configuration Register.

The number of Words to be output during a Syn-

chronous Burst Read operation can be configured

as 4 Words, 8 Words, 16 Words or Continuous

(Burst Length bits CR2-CR0). The data can be

configured to remain valid for one or two clock cy-

cles (Data Output Configuration bit CR9).

The order of the data output can be modified

through the Wrap Burst bit in the Configuration

can be confined inside the 4, 8 or 16 Word bound-

ary (Wrap) or overcome the boundary (No Wrap).

The WAIT signal may be asserted to indicate to

the system that an output delay will occur. This de-

lay will depend on the starting address of the burst

sequence and on the burst configuration.

WAIT is asserted during the X latency, the WAIT

state and at the end of a 4, 8 and 16 Word burst. It

is only de-asserted when output data are valid. In

Continuous Burst Read mode a WAIT state will oc-

cur when crossing the first 16 Word boundary. If

the starting address is aligned to the Burst Length

(4, 8 or 16 Words) the wrapped configuration has

no impact on the output sequence.

The WAIT signal can be configured to be active

Low or active High by setting CR10 in the Config-

uration Register.

See Table 24., Synchronous Read AC Character-

istics, and Figure 12., Synchronous Burst Read

AC Waveforms, for details.

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