M58LR128GT datasheet(28/84 Pages) STMICROELECTRONICS

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M58LR128GT, M58LR128GB

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chronous read operations. When the Valid Clock

Edge bit is Low (set to ’0’) the falling edge of the

Clock is the active edge. When the Valid Clock

Edge bit is High (set to ’1’) the rising edge of the

Clock is the active edge.

Wrap Burst Bit (CR3)

The Wrap Burst bit, CR3, is used to select be-

tween wrap and no wrap. Synchronous burst

reads can be confined inside the 4, 8 or 16 Word

boundary (wrap) or overcome the boundary (no

wrap).

When the Wrap Burst bit is Low (set to ‘0’) the

burst read wraps. When it is High (set to ‘1’) the

burst read does not wrap.

Burst length Bits (CR2-CR0)

The Burst Length bits are used to set the number

of Words to be output during a Synchronous Burst

Read operation as result of a single address latch

cycle.

They can be set for 4 Words, 8 Words, 16 Words

or continuous burst, where all the Words are read

sequentially. In continuous burst mode the burst

sequence can cross bank boundaries.

In continuous burst mode, in 4, 8 or 16 Words no-

wrap, depending on the starting address, the de-

vice asserts the WAIT signal to indicate that a de-

lay is necessary before the data is output.

If the starting address is aligned to an 8 Word

boundary no WAIT states are needed and the

WAIT output is not asserted.

If the starting address is not aligned to the 8 Word

boundary, WAIT will be asserted when the burst

sequence crosses the first 16 Word boundary to

indicate that the device needs an internal delay to

read the successive Words in the array.

WAIT will be asserted only once during a continu-

ous burst access. See also Table 12., Burst Type

Definition.

CR14, CR5 and CR4 are reserved for future use.

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