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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8720 датащи(PDF) 6 Page - Texas Instruments |
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LP8720 датащи(HTML) 6 Page - Texas Instruments |
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6 / 26 page  LP8720 SNVS575B – JULY 2008 – REVISED MAY 2013 www.ti.com Table 2. Default Output Voltages(1)(2) Output Max Current [mA] Default output Voltage [V] and default ON/OFF if EN=HI DEFSEL=VBATT DEFSEL=GND DEFSEL=Hi-Z LDO1 300 3.0 ON 3.0 OFF 2.8 ON LDO2 300 2.6 ON 3.0 OFF 2.6 ON LDO3 300 1.8 ON 2.6 ON 1.8 ON LDO4 300 1.0 ON 2.6 OFF 1.2 ON LDO5 300 3.3 OFF 3.3 OFF 3.3 OFF BUCK 400 1.0 OFF 1.2/1.31) OFF 1.2 OFF (1) BUCK voltage is 1.2V if DVS=LO and 1.3V if DVS=HI. (2) When IDSEL= VBATT then slave address is 7h’7F When IDSEL= floating (Hi-Z) then slave address is 7h’7C When IDSEL= GND then slave address is 7h’7D Table 3. Control Register Map(1) POR default DEFSEL Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VBATT GND Hi-Z GENERAL_ EXT_DVS_ EXT_SLEEP_ SHORT_ 0x00 0000 0001 0000 0101 0000 0001 SETTINGS CONTROL CONTROL TIMESTEP LDO1_ LDO1_ LDO1_ LDO1_ LDO1_ LDO1_ LDO1_ LDO1_ LDO1_ 0x01 0111 1101 1111 1101 0111 1001 SETTINGS T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO2_ LDO2_ LDO2_ LDO2_ LDO2_ LDO2_ LDO2_ LDO2_ LDO2_ 0x02 0111 0101 1111 1101 0111 0101 SETTINGS T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO3_ LDO3_ LDO3_ LDO3_ LDO3_ LDO3_ LDO3_ LDO3_ LDO3_ 0x03 0110 1100 0111 0101 0110 1100 SETTINGS T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO4_ LDO4_ LDO4_ LDO4_ LDO4_ LDO4_ LDO4_ LDO4_ LDO4_ 0x04 0110 0011 1111 1010 0110 0101 SETTINGS T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] LDO5_ LDO5_ LDO5_ LDO5_ LDO5_ LDO5_ LDO5_ LDO5_ LDO5_ 0x05 1111 1111 1111 1111 1111 1111 SETTINGS T[2] T[1] T[0] V[4] V[3] V[2] V[1] V[0] BUCK_ BUCK_ BUCK_ BUCK_ BUCK_ BUCK_ BUCK_ BUCK_ BUCK_ 0x06 1110 0101 1110 1011 1110 1001 SETTINGS1 T[2] T[1] T[0] V1[4] V1[3] V1[2] V1[1] V1[0] BUCK_ FORCE_ BUCK_ BUCK_ BUCK_ BUCK_ BUCK_ 0x07 0000 0101 0000 1001 0000 1001 SETTINGS2 PWM V2[4] V2[3] V2[2] V2[1] V2[0] ENABLE_ DVS_ SLEEP_ BUCK_ LDO5_ LDO4_ LDO3_ LDO2_ LDO1_ 0x08 1000 1111 1000 0100 1000 1111 BITS V2/V1 MODE EN EN EN EN EN EN PULLDOWN_ APU_ BUCK_ LDO5_ LDO4_ LDO3_ LDO2_ LDO1_ 0x09 0011 1111 0011 1111 0011 1111 BITS TSD PULLDOWN PULLDOWN PULLDOWN PULLDOWN PULLDOWN PULLDOWN STATUS_ 0x0A TSD TSD_EW 0000 0000 0000 0000 0000 0000 BITS INTERRUPT_ TSD_ TSD_EW_ 0x0B 0000 0000 0000 0000 0000 0000 BITS (2) INT INT INTERRUPT_ TSD_ TSD_EW_ 0x0C 0000 0011 0000 0011 0000 0011 MASK (2) MASK MASK (1) When IDSEL= VBATT then slave address is 7h’7F. When IDSEL= floating (Hi-Z) then slave address is 7h’7C. When IDSEL= GND then slave address is 7h’7D. (2) Registers STATUS_BITS 0x0A and INTERRUPT_BITS 0x0B are read only. 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LP8720 |
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