LP8720

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SNVS575B – JULY 2008 – REVISED MAY 2013

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Slave sends acknowledge signal.

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If master will send further data bytes the control register address will be incremented by one after

acknowledge signal.

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Write cycle ends when the master creates stop condition.

Control Register Read Cycle

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Master device generates a start condition.

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Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

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Slave device sends acknowledge signal if the slave address is correct.

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Master sends control register address (8 bits).

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Slave sends acknowledge signal.

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Master device generates repeated start condition.

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Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).

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Slave sends acknowledge signal if the slave address is correct.

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Slave sends data byte from addressed register.

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If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

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Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Address Mode

Data Read

<Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Repeated Start Condition>

<Slave Address><r/w = ‘1’>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent register address possible

<Stop Condition>

Data Write

<Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent register address possible

<Stop Condition>

< > Data from master [ ] Data from slave

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