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M68HC08 датащи(PDF) 63 Page - Freescale Semiconductor, Inc |
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M68HC08 датащи(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 172 page ![]() Exception Control MC68HC908JL3E Family Data Sheet, Rev. 3 Freescale Semiconductor 63 5.5.2.1 Interrupt Status Register 1 IF1, IF3 to IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 5-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3 and 7 — Always read 0 5.5.2.2 Interrupt Status Register 2 Table 5-3. Interrupt Sources Priority Source Flag Mask1(1) INT Register Flag Vector Address Highest Reset — — — $FFFE–$FFFF SWI Instruction — — — $FFFC–$FFFD IRQ1 Pin IRQF1 IMASK1 IF1 $FFFA–$FFFB Timer Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7 Timer Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5 Timer Overflow Interrupt TOF TOIE IF5 $FFF2–$FFF3 Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1 Lowest ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF 1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction. Address: $FE04 Bit 7 654321 Bit 0 Read: 0 IF5 IF4 IF3 0 IF1 0 0 Write: RRRRRRRR Reset: 00000000 R= Reserved Figure 5-12. Interrupt Status Register 1 (INT1) Address: $FE05 Bit 7 654321 Bit 0 Read: IF14 0000000 Write: RRRRRRRR Reset: 00000000 R= Reserved Figure 5-13. Interrupt Status Register 2 (INT2) |
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