M68HC08 datasheet(36/172 Pages) FREESCALE

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Configuration Registers (CONFIG)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

LVID — Low Voltage Inhibit Disable Bit

1 = Low Voltage Inhibit disabled

0 = Low Voltage Inhibit enabled

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of

× 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay.

1 = Stop mode recovery after 32

× 2OSCOUT cycles

0 = Stop mode recovery after 4096

× 2OSCOUT cycles

NOTE

Exiting stop mode by pulling reset will result in the long stop recovery.

If using an external crystal, do not set the SSREC bit.

STOP — STOP Instruction Enable

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).)

1 = COP module disabled

0 = COP module enabled

3.4 Configuration Register 2 (CONFIG2)

IRQPUD — IRQ1 Pin Pull-up control bit

1 = Internal pull-up is disconnected

0 = Internal pull-up is connected between IRQ1 pin and VDD

LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits

Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI)

Address:

$001E

Bit 7

654321

Bit 0

Read:

IRQPUD

LVIT1

LVIT0

RRR

Write:

Reset:

000

Not

affected

Not

affected

000

POR:

00000000

R= Reserved

Figure 3-2. Configuration Register 2 (CONFIG2)

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