LMK02002

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SNAS418 – AUGUST 2007

When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt.

GLOBAL OUTPUT ENABLE AND LOCK DETECT

The GOE pin provides an internal pull-up resistor. If it is not terminated externally, the clock output states are

determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit.

By programming the PLL_MUX register to Digital Lock Detect Active High (See PLL_MUX[3:0] -- Multiplexer

Control for LD Pin), the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set

low automatically if the synthesizer is not locked.

POWER ON RESET

When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets

all registers to their default values, see RESET bit -- R0 only for more information on default register values.

Voltage should be applied to all Vcc pins simultaneously.

General Programming Information

The LMK02002 device is programmed using several 32-bit registers which control the device's operation. The

registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field.

The remaining 28 bits form the data field DATA[27:0].

During programming, LEuWire is low and serial data is clocked in on the rising edge of clock (MSB first). When

LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers R0 to

R7, R11, R14, and R15 need to be programmed for proper device operation.

It is required to program register R14.

RECOMMENDED PROGRAMMING SEQUENCE

The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to

ensure the device is in a default state. It is not necessary to program R0 again. Registers are programmed in

order with R15 being the last register programmed. An example programming sequence is shown below.

•

Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state.

•

Program R4 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings.

•

Program R11 with DIV4 setting if necessary.

•

Program R14 with global clock output bit, power down setting, PLL mux setting, and PLL R divider. It is

required to program register R14.

–

R14 must be programmed in accordance with the register map as shown in the register map (see

Table 1).

•

Program R15 with PLL charge pump gain, and PLL N divider.

Copyright © 2007, Texas Instruments Incorporated

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