LMK02002

www.ti.com

SNAS418 – AUGUST 2007

Electrical Characteristics

(1) (continued)

(3.15 V

≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most

likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product

characterization and are not specified).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PLL_CP_GAIN = 1x

-219

PN1Hz

Normalized Phase Noise Contribution(6)

dBc/Hz

PLL_CP_GAIN = 32x

-224

Clock Distribution Section (7) - LVPECL Clock Outputs (CLKout0 to CLKout3)

CLKoutX_MUX =

20

RL = 100 Ω

Bypass

Distribution Path =

CLKoutX_MUX =

JitterADD

Additive RMS Jitter (7)

800 MHz

fs

Divided

Bandwidth =

75

CLKoutX_DIV =

12 kHz to 20 MHz

4

Equal loading and identical clock

tSKEW

CLKoutX to CLKoutY (4)

configuration

-30

±3

30

ps

Termination = 50

Ω to Vcc - 2 V

Vcc -

VOH

Output High Voltage

V

0.98

Termination = 50

Ω to Vcc - 2 V

Vcc -

VOL

Output Low Voltage

CLKoutX output frequency = 200 MHz

V

1.8

VOD

Differential Output Voltage

660

810

965

mV

Digital LVTTL Interfaces (8)

VIH

High-Level Input Voltage

2.0

Vcc

V

VIL

Low-Level Input Voltage

0.8

V

IIH

High-Level Input Current

VIH = Vcc

-5.0

5.0

µA

IIL

Low-Level Input Current

VIL = 0

-40.0

5.0

µA

Vcc -

VOH

High-Level Output Voltage

IOH = +500 µA

V

0.4

VOL

Low-Level Output Voltage

IOL = -500 µA

0.4

V

Digital MICROWIRE Interfaces (9)

VIH

High-Level Input Voltage

1.6

Vcc

V

VIL

Low-Level Input Voltage

0.4

V

IIH

High-Level Input Current

VIH = Vcc

-5.0

5.0

µA

IIL

Low-Level Input Current

VIL = 0

-5.0

5.0

µA

MICROWIRE Timing

tCS

Data to Clock Set Up Time

See Data Input Timing

25

ns

tCH

Data to Clock Hold Time

See Data Input Timing

8

ns

tCWH

Clock Pulse Width High

See Data Input Timing

25

ns

tCWL

Clock Pulse Width Low

See Data Input Timing

25

ns

tES

Clock to Enable Set Up Time

See Data Input Timing

25

ns

tCES

Enable to Clock Set Up Time

See Data Input Timing

25

ns

tEWH

Enable Pulse Width High

See Data Input Timing

25

ns

(6)

A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined

as PN1Hz = LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a

1 Hz Bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure

LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid

a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be masked by the reference oscillator performance if

a low power or noisy source is used.

(7)

The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the

clock distribution section only.

(8)

Applies to GOE, LD, and SYNC*.

(9)

Applies to CLKuWire, DATAuWire, and LEuWire.

Copyright © 2007, Texas Instruments Incorporated

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