TDA7546 datasheet(31/68 Pages) STMICROELECTRONICS

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TDA7546

Functional description

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synchronization control. A software reset “ar_res” rds_int[5] can be used to force

resynchronization.

An endless 2 bit block counter (A, B, C or C’, D, A, B...) increments one step if a new RDS

block was received. During synchronization the block counter is set to the first identified

valid RDS block. Then every next RDS block must be of that type which is indicated by the

block counter “blk” rds_qu[3:2]. If this is not true, then the syndrome becomes not zero

(indicated by “synz” bit rds_qu[0]) and the “data_ok” bit rds_corrp[1] is not set. In case of

USA BRDS, four consecutive E blocks can be received which are indicated by the “e” bit

rds_qu[1].

The quality bit counter rds_qu[7:4] counts the bad quality marked RDS bits within a RDS

block.

The group and block synchronization module extracts also TA, TAEON information and

detects blocks types A, B, D (refer to Table 37) which can be used as interrupt sources.

The TA interrupt is performed in two cases: If within block B the group 0A or 0B is indicated

and the TA bit is set or if within block B group 15B is indicated and the TA bit is set. The

TAEON interrupt is performed, if within block B group 14B is indicated and the TA bit is set.

The interrupts can be recognized on the interrupt flag “int” rds_int[0] (refer to Table 37). The

external open drain pin INTN (15) is the inverted version of the “int” flag.

5.2.6

Flywheel mechanism

Figure 7.

Example for flywheel mechanism

Within group and block synchronization control block a 6 bit (64 states) flywheel counter is

implemented to control RDS synchronization. After reset or a forced resynchronization by

setting “ar_res” bit rds_int[5], this counter increments from zero to one, if a valid RDS block

was detected. Valid means the syndrome has to be zero (“synz” = 1 rds_qu[0]) without any

100

Signal

quality [%]

63(max)

Flywheel

counter

1.)

2.)

3.)

data_ok

synch

bne

interrupt

time

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