TDA7546 datasheet(59/68 Pages) STMICROELECTRONICS

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TDA7546

Software specifications

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6.3.3

SPI mode

Figure 18.

SPI data transfer

This interface consists of four lines (Figure 18). A serial data input (DATAIN), a serial data

output (DATAOUT), a chip select input (CSN) and a bit clock input (CLK).

The interface is capable of operating up to 1 MHz. If during the setup the system clock fsys

is smaller then 8.55 MHz, then the max. SPI speed decreases linear (e.i. if fsys = 4.275 MHz

then the maximum SPI speed is 500KHz for setup).

CSN starts and stops the data transfer. After starting data transfer, one bit is shifted out

(DATAOUT) with the active bit clock edge (CLK) and at the same time one bit in (DATAIN).

When CSN stops the data transfer, the pllreg0[7:0], pllreg1[7:0] pllreg2[7:0], pllreg3[7:0],

pllreg4[7:0], rdstest[7:0], sinc4reg[7:0], rds_bd_ctrl[7:0], rds_int[7:0] registers can be

updated with the last bytes which have been shifted in.

The last byte shifted in on DATAIN must be always rds_int[7:0] and the last but one is

rds_bd_ctrl[7:0], and so on, as listed above. In other words, the master has take into

account the number of bytes to transfer before starting, to be sure that the last byte shifted in

at DATAIN is rds_int[7:0].

If the pllreg0[7:0], pllreg1[7:0] pllreg2[7:0], pllreg3[7:0], pllreg4[7:0], rdstest[7:0],

sinc4reg[7:0], rds_bd_ctrl[7:0], rds_int[7:0] registers will be updated depends on the MSB of

rds_int. If rds_int[7] = 1 all registers listed above are updated (refer to page 48). The

registers pllreg3-1 are only updated if they are shifted completely into the SPI.

sinc4reg[7:0] and testreg[7:0] are dedicated for test and have to be kept zero filled in the

application, independent if rds_int[7] bit is set or not.

Only the “bne” flag can be used for polling mode. There are two different ways to use

polling mode, while the first one causes less bus traffic than the second:

Read only the first register rds_int to check the “bne” bit.

If “bne” bit is not set, the CSN can be set, as shown in (Figure 21).

If “bne” bit is set, the transfer must be continued by the SPI master, until at least the

four register rds_qu, rds_corrp, rds_bd_h and rds_bd_l are read out, then the SPI

master is allowed to stop the transfer by pulling CSN up. Then the whole Buffer must be

read out, by reading each time at least the five registers rds_int, rds_qu, rds_corrp,

CSN

DATAIN

DATAOUT

CLK

rds_int[7:0]

rds_qu[7:0]

rds_corrp[7:0]

rds_bd_h[7:0]

rds_bd_l[7:0]

{1,rds_int[6:0]}

rds_bd_ctrl[7:0]

sinc4reg[7:0]

testreg[7:0]

pll_reg4l[7:0]

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