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S29GL01GS датащи(PDF) 80 Page - Cypress Semiconductor

номер детали S29GL01GS
подробное описание детали  1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte),3.0 V, GL-S Flash Memory
PDF  108 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S29GL01GS датащи(HTML) 80 Page - Cypress Semiconductor

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Document Number: 001-98285 Rev. *R
Page 80 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Note:
1. Not 100% tested.
Figure 11.5 Back to Back Read (tACC) Operation Timing Diagram
Figure 11.6 Back to Back Read Operation (tRC)Timing Diagram
Note:
Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access.
tPACC
Page Access Time
128 Mb, 256 Mb
Max
25
30
–
ns
512 Mb, 1 Gb
–
25
30
tGLQV
tOE
Output Enable to Output Delay
Max
35
ns
tAXQX
tOH
Output Hold time from addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
tEHQZ
tDF
Chip Enable or Output Enable to Output
High-Z (Note 1)
Max
20
ns
tOEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
tASSB
Automatic Sleep to Standby time (Note 1)
CE# = VIL, Address
stable
Typ
5
µs
Max
8
µs
Table 11.6 Read Operation VIO = 1.65 V to VCC, VCC = 2.7 V to 3.6 V (–40 °C to +105 °C) (Continued)
Parameter
Description
Test Setup
Speed Option
Unit
JEDEC
Std
110
120
130
Amax-A0
CE#
OE#
DQ15-DQ0
tACC
tOE
tCE
tDF
tDF
tOH
tOH
tOH
Amax-A0
CE#
OE#
DQ15-DQ0
tRC
tACC
tOE
tCE
tDF
tOH
tOH



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