WM8994ECSSLASHR datasheet(288/363 Pages) CIRRUS

288 / 363 page

WM8994

288

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

010 = 4

011 = 8

1XX = 16

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R546 (0222h)

FLL1 Control

(3)

15:0

FLL1_K [15:0]

0000_0000

_0000_000

FLL1 Fractional multiply for FREF

(MSB = 0.5)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R547 (0223h)

FLL1 Control

(4)

14:5

FLL1_N [9:0]

00_0000_0

000

FLL1 Integer multiply for FREF

(LSB = 1)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R548 (0224h)

FLL1 Control

(5)

12:7

FLL1_FRC_NC

O_VAL [5:0]

01_1001

FLL1 Forced oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for free-running FLL modes

only)

FLL1_FRC_NC

FLL1 Forced control select

0 = Normal

1 = FLL1 oscillator controlled by FLL1_FRC_NCO_VAL

(Note that this field is required for free-running FLL modes

only)

4:3

FLL1_REFCLK_

DIV [1:0]

FLL1 Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must be divided down to

<=13.5MHz.

For lower power operation, the reference clock can be

divided down further if desired.

1:0

FLL1_REFCLK_

SRC [1:0]

FLL1 Clock source

00 = MCLK1

01 = MCLK2

10 = LRCLK1

11 = BCLK1

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