WM8994ECSSLASHR datasheet(287/363 Pages) CIRRUS

287 / 363 page

WM8994

Rev 4.6

287

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R530 (0212h)

Rate Status

3:0

SR_ERROR

[3:0]

0000

Sample Rate Configuration status

Indicates an error with the register settings related to

sample rate configuration

0000 = No errors

0001 = Invalid sample rate

0010 = Invalid AIF divide

0011 = ADC and DAC divides both set in an interface

0100 = Invalid combination of AIF divides and sample-rate

0101 = Invalid set of enables for 96kHz mode

0110 = Invalid SYSCLK rate (derived from AIF1CLK_RATE

or AIF2CLK_RATE)

0111 = Mixed ADC and DAC rates in SYSCLK AIF when

AIFs are asynchronous

1000 = Invalid combination of sample rates when both AIFs

are from the same clock source

1001 = Invalid combination of mixed ADC/DAC AIFs when

both from the same clock source

1010 = AIF1DAC2 (Timeslot 1) ports enabled when SRCs

connected to AIF1

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R544 (0220h)

FLL1 Control

(1)

FLL1_OSC_EN

FLL1 Oscillator enable

0 = Disabled

1 = Enabled

(Note that this field is required for free-running FLL1 modes

only)

FLL1_ENA

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the FLL1 enable

sequence, ie. after the other FLL registers have been

configured.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R545 (0221h)

FLL1 Control

(2)

13:8

FLL1_OUTDIV

[5:0]

00_0000

FLL1 FOUT clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(FOUT = FVCO / FLL1_OUTDIV)

2:0

FLL1_FRATIO

[2:0]

000

FLL1 FVCO clock divider

000 = 1

001 = 2

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