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WM8994ECS/R датащи(PDF) 183 Page - Cirrus Logic

номер детали WM8994ECS/R
подробное описание детали  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R датащи(HTML) 183 Page - Cirrus Logic

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WM8994
Rev 4.6
183
AIF2 CLOCK OUTPUT CONTROL
BCLK2
(GPIO3)
enable
AIF2CLK
/AIF2_BCLK_DIV
AIF2DAC_LRCLK_DIR
BCLK2
enable
/AIF2DAC_RATE
LRCLK2
(GPIO4)
AIF2DACL_ENA
AIF2DACR_ENA
AIF2ADCL_ENA
AIF2ADCR_ENA
GP6_FN != 0
AIF2_CLK_FRC
AIF2ADC_LRCLK_DIR
GP6_FN != 0
AIF2_CLK_FRC
AIF2_MSTR
AIF2_LRCLK_FRC
AIF2_MSTR
AIF2_MSTR
AIF2ADC_LRCLK_DIR
BCLK2
enable
/AIF2ADC_RATE
ADCLRCLK2
(GPIO6)
AIF2_CLK_FRC
AIF2ADCL_ENA
AIF2ADCR_ENA
AIF2_LRCLK_FRC
GP6_FN = 0
Note: GPIO6 is configured as
ADCLRCLK2 when GP6_FN = 0
Note: LRCLK2 provides clocking
for the DAC and ADC channels of
AIF2 when GP6_FN != 0
Figure 65 Audio Interface 2 - BCLK and LRCLK Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R784 (0310h)
AIF2 Control
(1)
8
AIF2_BCLK
_INV
0
BCLK2 Invert
0 = BCLK2 not inverted
1 = BCLK2 inverted
Note that AIF2_BCLK_INV selects the BCLK2
polarity in Master mode and in Slave mode.
7
AIF2_LRCL
K_INV
0
Right, left and I2S modes
– LRCLK2 polarity
0 = normal LRCLK2 polarity
1 = invert LRCLK2 polarity
Note that AIF2_LRCLK_INV selects the
LRCLK2 polarity in Master mode and in Slave
mode.
DSP Mode
– mode A/B select
0 = MSB is available on 2nd BCLK2 rising
edge after LRCLK2 rising edge (mode A)
1 = MSB is available on 1st BCLK2 rising
edge after LRCLK2 rising edge (mode B)



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