WM8994ECSSLASHR datasheet(182/363 Pages) CIRRUS

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WM8994

182

Rev 4.6

AIF2 - SIGNAL PATH ENABLE

The AIF2 interface supports two input channels and two output channels. Each of the available

channels can be enabled or disabled using the register bits defined in Table 96.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (0004h)

Power

Management

(4)

AIF2ADCL_

ENA

Enable AIF2ADC (Left) output path

0 = Disabled

1 = Enabled

AIF2ADCR_

ENA

Enable AIF2ADC (Right) output path

0 = Disabled

1 = Enabled

R5 (0005h)

Power

Management

(5)

AIF2DACL_

ENA

Enable AIF2DAC (Left) input path

0 = Disabled

1 = Enabled

AIF2DACR_

ENA

Enable AIF2DAC (Right) input path

0 = Disabled

1 = Enabled

Table 96 AIF2 Signal Path Enable

AIF2 - BCLK AND LRCLK CONTROL

he BCLK2 frequency is controlled relative to AIF2CLK by the AIF2_BCLK_DIV divider. See “Clocking

and Sample Rates

” for details of the AIF2 clock, AIF2CLK.

The LRCLK2 frequency is controlled relative to BCLK2 by the AIF2DAC_RATE divider.

In Master mode, the LRCLK2 output is generated by the WM8994 when any of the AIF2 channels is

enabled. (Note that, when GPIO6 is configured as ADCLRCLK2, then only the AIF2 DAC channels will

cause LRCLK2 to be output.)

In Slave mode, the LRCLK2 output is disabled by default to allow another digital audio interface to

drive this pin. It is also possible to force the LRCLK2 signal to be output, using the

AIF2DAC_LRCLK_DIR or AIF2ADC_LRCLK_DIR register bits, allowing mixed master and slave

modes. (Note that, when GPIO6 is configured as ADCLRCLK2, then only the AIF2DAC_LRCLK_DIR

bit will force the LRCLK2 signal.)

When the GPIO6 pin is configured as ADCLRCLK2, then the ADCLRCLK2 frequency is controlled

relative to BCLK2 by the AIF2ADC_RATE divider. In this case, the ADCLRCLK2 is dedicated to AIF2

output, and the LRCLK2 pin is dedicated to AIF2 input, allowing different sample rates to be supported

in the two paths.

In Master mode, with GPIO6 pin configured as ADCLRCLK2, this output is enabled when any of the

AIF2 ADC channels is enabled. The ADCLRCLK2 signal can also be enabled in Slave mode, using

the AIF2ADC_LRCLK_DIR bit, allowing mixed master and slave modes.

See “General Purpose Input/Output” for the configuration of GPIO6.

The BCLK2 output can be inverted using the AIF2_BCLK_INV register bit. The LRCLK2 and

ADCLRCLK2 output (when selected) can be inverted using the AIF2_LRCLK_INV register control.

Note that in Slave mode, when BCLK2 is an input, the AIF2_BCLK_INV register selects the polarity of

the received BCLK2 signal. Under default conditions, DACDAT2 input is captured on the rising edge

of BCLK2, as illustrated in Figure 5. When AIF2_BCLK_INV = 1, DACDAT2 input is captured on the

falling edge of BCLK2.

The AIF2 clock generators are controlled as illustrated in Figure 65.

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