MP86992

– 50A INTELLI-PHASETM SOLUTION IN LGA (5MMX6MM)

MP86992 Rev. 1.0

www.MonolithicPower.com

11

11/5/2019

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PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation. For best results, refer to Figure 4 and

follow the guidelines below:

1. Place the input MLCC capacitors as close to

VIN and PGND as possible.

2. Place the major MLCC capacitors on the

same layer as the MP86992.

3. Place

as

many VIN

and

PGND

vias

underneath the package as possible.

4. Place the vias between the VIN or PGND

long pads.

5. Place a VIN copper plane on the second

inner layer to form the PCB stack as

positive/negative/positive

to

reduce

the

parasitic impedance from the input MLCC

capacitor to the MP86992.

6. Ensure that the copper plane on the inner

layer covers at least the VIN vias underneath

the package and the input MLCC capacitors.

7. Place more PGND vias close to the PGND

pin/pad

to

minimize

both

parasitic

resistance/impedance

and

thermal

resistance.

8. Place the BST and VDRV capacitors as

close to the MP86992

’s pins as possible.

9. Use a trace width of 20 mils or higher to route

the path.

10. Avoid placing vias on the BST driving path.

11. Use a 0.1µF to 1µF bootstrap capacitor.

12. Place the VDD decoupling capacitor close to

the device.

13. Connect AGND and PGND at the point of the

VDD capacitor

’s ground connection.

14. Keep the IOUT signal trace away from high-

current paths, such as SW and PWM.

PGND

40

41

Figure 4: Recommended PCB Layout (Placement and Top Layer PCB)

Input Capacitor: 0805 package (top and bottom sides) and 0402 package (top side)

Inductor: 11x8 package

VDD/BST/VDRV capacitor: 0402 package

Via size: 20/10 mils