MP86992

– 50A INTELLI-PHASETM SOLUTION IN LGA (5MMX6MM)

MP86992 Rev. 1.0

www.MonolithicPower.com

3

11/5/2019

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© 2019 MPS. All Rights Reserved.

PIN FUNCTIONS

Pin #

Pin Name

Descriptions

1, 6, 31,

37, 39, 41

NC

No connection.

2

AGND

Analog ground.

3

VDD

Supply voltage for internal circuitry.

Connect VDD to VDRV through a 2.2Ω

resistor. Decouple VDD with a 1µF capacitor to AGND. Connect AGND and PGND

at the VDD capacitor.

4

VDRV

Driver voltage. Connect VDRV to a 3.3V supply. Decouple VDRV with a 1µF to

4.7µF ceramic capacitor.

5, 7, 8, 9,

20

–24, 40

PGND

Power ground.

10

–19

SW

Phase node.

25

–30

VIN

Input supply voltage. Place input ceramic capacitors (CIN) close to the device to

support the switching current with minimal parasitic inductance.

32

PHASE

Switching node for the bootstrap capacitor connection. The PHASE pin is

connected to SW internally.

33

BST

Bootstrap.

BST requires a 0.1µF to 0.22µF capacitor to drive the power switch’s

gate above the supply voltage. Connect the capacitor between SW and BST to

form a floating supply across the power switch driver.

34

PWM

Pulse-width modulation input. Leave PWM floating or drive PWM to a mid-state

level to put SW in a high-impedance state.

35

EN

Enable. Pull EN low to disable the MP86992 and place SW in a high-impedance

state.

36

TOUT/FLT

Single-pin temperature sense and fault reporting. TOUT/FLT is pulled up to

the VDD voltage when a fault occurs.

38

IOUT

Current-sense output. Use an external resistor to adjust the voltage proportional

to the inductor current.

ABSOLUTE MAXIMUM RATINGS (1)

VIN to PGND................................. -0.3V to +25V

VIN to VSW..................................... -0.3V to +25V

VIN to VSW (10ns)..........................................32V

VSW to PGND................................ -0.3V to +21V

VSW to PGND (25ns)........................ -5V to +25V

VBST .....................................................VSW + 4V

VDD, VDRV........................................ -0.3V to +4V

All other pins......................-0.3V to VDD + 0.3V

Instantaneous current ...............................110A

Junction temperature ............................... 150°C

Lead temperature .................................... 260°C

Storage temperature ................ -65°C to +150°C

Recommended Operating Conditions (2)

Supply voltage (VIN) ........................ 3.0V to 16V

Driver voltage (VDRV) ................... 3.0V to 3.6V

Logic voltage (VDD)....................... 3.0V to 3.6V

Operating junction temp (TJ) .... -40°C to +125°C

Thermal Resistance (3)

θJB θJC_TOP

LGA-41 (5mmx6mm)............2.2...... 8.7 .... °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) The device is not guaranteed to function outside of its operating

conditions.

3)

θ

JB: Thermal resistance from the junction to board around the

PGND soldering point.

θ

JC_TOP: Thermal resistance from the junction to the top of the

package.