LPC2292 datasheet(25/54 Pages) PHILIPS

25 / 54 page

LPC2292_2294_6

Product data sheet

Rev. 06 — 10 December 2007

25 of 54

NXP Semiconductors

LPC2292/LPC2294

16/32-bit ARM microcontrollers with external memory interface

• Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must ‘release’ new match values before they can become

effective.

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

6.19 System control

6.19.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output

frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for

purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is

running and connected. Refer to Section 6.19.2 “PLL” for additional information.

6.19.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100

µs.

6.19.3 Reset and wake-up timer

Reset has two sources on the LPC2292/2294: the RESET pin and watchdog reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of chip

reset by any source starts the Wake-up Timer (see Wake-up Timer description below),

causing the internal chip reset to remain asserted until the external reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is

the reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power-on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

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