TC9328AF datasheet(19/84 Pages) TOSHIBA

19 / 84 page

TC9328AF

2004-09-13

Machine Language (16 bits)

Instruc

-tion

Group

Mnemonic

Skip

Function

Function Description

Operation Description

(6 bits)

(2 bits)

(4 bits)

r, M*

Load memory to

general register

← (M*)

0101

DR*

(4 bits)

M*, r

Store memory to

general register

← (r)

0110

DR*

(4 bits)

MVSR

M1, M2

Move memory to

memory in same row

(DR, DC1)

← (DR, DC2)

001111

DC1

DC2

MVIM

M, I

Move immediate data

to memory

← I

000111

MVGD r, M

Move memory to

destination memory

referring to G-register

and general register

[(G), (r)]

← (M)

011110

MVGS

M, r

Move source

memory referring to

G-register and

general register to

memory

(Note)

(M)

← [(G), (r)]

011111

STIG

Move immediate data

to G-register

← I*

111111

0010

IN1

M, C

Input IN1 port data to

memory

← [IN1] C

111000

OUT1

M, C

Output contents of

memory to OUT1

port

[OUT1] C

← (M)

111011

IN2

M, C

Input IN2 port data to

memory

← [IN2] C

111001

OUT2

M, C

Output contents of

memory to OUT2

port

[OUT2] C

← (M)

111100

IN3

M, C

Input IN3 port data to

memory

← [IN3] C

111010

OUT3

M, C

Output contents of

memory to OUT3

port

[OUT3] C

← (M)

111101

ORR

r, M

Logical OR of

general register and

memory

← (r) ∨ (M)

001100

ANDR

r, M

Logical AND of

general register and

memory

← (r) ∧ (M)

001101

ORIM

M, I

Logical OR of

memory and

immediate data

← (M) ∨ I

000100

ANIM

M, I

Logical AND of

memory and

immediate data

← (M) ∧ I

000101

XORIM M, I

Logical exclusive OR

of memory and

immediate data

← (M) ∀ I

000110

XORR

r, M

Logical exclusive OR

of general register

and memory

← (r) ∀ (M)

001110

Note: The execution period for the MVGS instruction is two machine cycles.

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