TC9328AF datasheet(67/84 Pages) TOSHIBA

67 / 84 page

TC9328AF

2004-09-13

Set up the pull-up and pull-down is used for key matrix configuration. I/O Port-1 with a pull down or a

pull-up is considered for a usual I/O Port output as an input as an output of a key matrix, and a key matrix

is configured. It is able to configure the key matrix of a low noise by the following methods. In setting

pull-down to I/O port-1, the output side of a key matrix is usually high impedance (input state), output and

scan to “H” level on key loaded line, detected key input or non by loading input status of I/O port-1. In the

case of a pull-up, “L” level is outputted and it detected on a key loading line. During executing of CKSTP

instruction and WAIT instruction, the existence of this key input can also be judged and restarted. When

restarting at the time of CKSTP command execution, I/O Port-1 is used by changing into a pull-up state.

For the clock stop mode, since the outputs of an I/O Port are outputted all “L” level, I/O Port-1 stands by in

the state of a pull-up, and if a key is inputted, I/O Port-1 input will change and restart. In this case, since

the standby time of about 100 ms occurs as time lag after being canceled of a clock stop. Since release of

WAIT instruction holds the output state, restarting is possible by the method of both a pull-up and a pull

down, and since there is no time lag from release, detection and operation of a key are quickly possible.

Using these backup modes together can reduce consumption current.

Since the input of I/O Port-1 is an inverter input, the usage that serves as middle potential cannot be

done to this input. But, only at the time of execution of the input instruction, since an input will be in an

ON state, even if middle potential is inputted, as for other I/O Port inputs, unusual consumption current

does not occur. For this reason, use of the pull-up in potential lower than VDD potential, the three value

output of an output level, etc. is possible.

I/O Port -2, -4 pins are the I/O Ports of CMOS structure, P2-3 pin is the prescaller PSC output, P4-0 pin

is the buzzer output and P4-1-3 pins are the serial interface serve a double purpose, respectively. I/O port-3,

-5~-9 are Nch open drain I/O port.

I/O Port -3 uses VLCD (3 V) for the gate potential of Nch output buffer. For this reason, the output

current by which power supply voltage was stabilized also in the time of low voltage can be obtained. This

port can perform the input and output to 3.6 V.

I/O port-5 is used as 6-bit A/D converter input. This port is able to inputted VDB potential (the potential

to VDD × 2).

I/O Port -8, -9 are also used as LCD driver. VLCD (3 V) is used for the gate potential of an Nch open

output buffer. For this reason, the output current by which power supply voltage was stabilized also in the

time of low voltage can be obtained. These pins can perform the input and output to VLCD (3 V). These pins

are set as the input of an I/O Port after reset.

Note: The data select port is

+1 increments automatically when it accesses φL2E, φL2F, φL3B, φK3B on the

I/Omap.

P1-3

VDD

P1-2

P1-1

P1-0

P9-3

P9-2

P9-1

P9-0

Example for key input matrix circuit

configuration

P9-3

P9-2

P9-1

P9-0

High impedance

P1-3

P1-2

P1-1

P1-0

Pull-up

Pushing of P9-3 and P1-1 keys

I/O port-1

Loaded into data

The following is an example of key input matrix circuit

configuration. Without key input, it pulled-up and key is

pushed, it inputted “L” level from sauce side(I/O port-9).

It is necessary to take into consideration the shift time to

the pull-up of a key input from “L”. They are all about a key

sauce side at the time of WAIT instruction execution and

“L” WAIT instruction can be lifted, whenever a key input

will be pushed, if it stands by on the level.

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