TC9328AF datasheet(62/84 Pages) TOSHIBA

62 / 84 page

TC9328AF

2004-09-13

10-Hz intermittent output with 1 Hz intervals mode (mode D), if buzzer enable bit is set “1”, 50-ms

buzzer output and 50-ms buzzer pause will carry out 500-ms output, after that 500-ms pause output of

50-ms buzzer output and the 50-ms buzzer pause is carried out again, and this operation is repeated. A set

of “0” stops a buzzer output. At mode B, C, and D, a buzzer is in an output state, even if it sets “0” to buzzer

enable bit and it makes it stop, the buzzer of 50 ms is outputted and stops. In addition, a buzzer output

state can be judged according to the contents of a timer port. The timer port 10-Hz bit is “0”, buzzer is an

output state and it is in a pause state at the time of “1”.

The control of buzzer is accessed by the OUT 1 instruction for which [CN = AH, BH] has been specified in

the operand.

Buzzer Circuit Configuration

Buzzer Output Timing

Note: When making a buzzer output, it sets up an output state about P4-0 (set “1” to I/O control port)

BUZR (P4-0)

10 Hz

1 Hz

0.625 kHz~3 kHz

BF0~BF2

BM0~BM2

BEN

Buzzer output circuit

Multiplexer

Data set to BEN bit

Buzzer frequency

10 Hz

“1”

Buzzer output (mode B)

“0”

Buzzer output (mode A)

Buzzer output (mode C)

During a buzzer output, If “1” is set to BEN bit again, 50 ms extension will be

carried out.

Buzzer output (mode D)

50 ms

Period of buzzer frequency

output

50 ms

Period of non-output

The output state in mode C

Period of output

“1”

500 ms

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