ADBMS6821 datasheet(19/28 Pages) AD

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Data Sheet

ADBMS6821/ADBMS6822

THEORY OF OPERATION

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Rev. B | 19 of 28

RECEIVER COMMON-MODE BIAS

When not transmitting, the output driver maintains IP and IM near

an internal bias voltage with a pair of RIN resistors to a voltage of

VCM. This weak bias network holds the outputs near their required

operating point without significantly loading the cable, which allows

transceivers to be paralleled without affecting signal amplitude.

When the transceiver is in the low-power idle mode, the bias

voltage is disconnected from the RIN resistors, which results in IP

and IM as a floating input.

Figure 37. Receiver Common-Mode Bias

SPI CONFIGURATION

The ADBMS6821/ADBMS6822 transceivers interface with a SPI

port on another device using four connections: CS, SCK, POCI,

and PICO. The transceiver can be configured to operate on the

controller end of a link (for example, connected to a microcontroller)

or on the peripheral end of a link (for example, connected to a

standalone analog-to-digital converter (ADC)). That operation is set

using the MSTR pin. In controller mode (MSTR = 1), CS, SCK, and

PICO are inputs and POCI is a push/pull output. In peripheral mode

(MSTR = 0), CS, SCK, and PICO are push/pull outputs and POCI is

an input.

The VDDS power supply pin is used for SPI input or output.

Connect VDDS to the same power supply that is used to power the

SPI port of the connected devices.

The POCI output of the transceiver is set to tristate and the output

is resistively pulled up to VDDS when in controller mode (MSTR =

1) and the SPI port is not selected (CS = 1). In this case, POCI

is pulled up to VDDS through an internal 1 MΩ resistor. Upon

activation or deactivation of the LPCM feature, the 1 MΩ resistor

mitigates the possibility of driving the POCI pin externally and

internally when switching between controller and peripheral mode.

SETTING CLOCK PHASE AND POLARITY

SPI devices often use one clock edge to latch data and the other

edge to shift data to avoid timing problems associated with clock

skew. SPI devices can be configured to idle SCK either high or low

and can also be configured to latch on either rising or falling clock

edge. The transceiver supports all four SPI phase/polarity operating

modes, configured by the PHAPOL pin.

The configuration of the PHAPOL pin is only detected and stored

in the memory after power-up of the VDDS pin. Changing the

PHAPOL pin configuration during operation does not affect SPI

phase/polarity operating mode. The initial detection of the PHAPOL

pin state does not occur while the transceiver is in the idle state.

Thus, upon first application of the VP or VDD supply, the transceiv-

er defaults to PHA = 1 and POL = 1 if the transceiver is left in the

idle state while the VDDS supply is applied. In this case, wake the

transceiver to the ready state to cause the PHAPOL pin state to be

detected. For more information, see the Idle Mode and Wake-Up

Detection section.

The four configuration settings for PHAPOL are shown in Table 20.

Table 20. PHAPOL SPI Modes

SPI Mode POL

PHA

Description

PHAPOL Pin

Connection

SCK idles low, latches on

rising (first) edge

GND

SCK idles low, latches on

falling (second) edge

20 kΩ resistor to

GND

SCK idles high, latches on

falling (first) edge

100 kΩ resistor to

GND

SCK idles high, latches on

rising (second) edge

VDDS

The two most common configurations are Mode 0 and Mode 3,

because these modes latch data on a rising clock edge. The

ADBMS battery monitors use SPI Mode 3.

TRANSCEIVER MODES

The ADBMS6821/ADBMS6822 transceivers have several modes

to allow enhanced capabilities with different system configurations.

The transceiver mode is set by the connection to the XCVRMD pin,

as shown in Table 21.

For communication with ADBMS battery monitors, one of the two

standard bidirectional isoSPI modes must be used. If the transceiv-

er is to be used as the timeout monitor in an ADBMS system with

LPCM capability, use the transceiver mode with timeout monitor

support.

The 4 Mbps unidirectional and 2 Mbps with 1-bit latency modes

do not work with ADBMS peripheral devices. They are intended

for communications between two microcontrollers or between a

microcontroller and non-BMS peripherals. Note that the transceiver

in controller mode (MSTR = 1) can be used to communicate

with the ADBMS stack monitor peripherals at 2 MHz even when

the XCVRMD pin connection is for standard bidirectional isoSPI

(connected to GND or 20 kΩ resistor to GND).

The configuration of the XCVRMD pin is checked upon the state

transition from IDLE to READY. Changing the XCVRMD pin config-

uration during operation does not affect the transceiver operating

mode without first returning to the IDLE state. The initial detection

of the XCVRMD pin state does not occur while the transceiver is in

the idle state. Thus, upon first application of the VP or VDD supply,

the transceiver defaults to standard bidirectional isoSPI with LPCM

timeout monitor support if the transceiver is left in the idle state

while the VDDS supply is applied. In this case, wake the transceiver

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