ADBMS6821 datasheet(16/28 Pages) AD

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Data Sheet

ADBMS6821/ADBMS6822

THEORY OF OPERATION

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Rev. B | 16 of 28

The ADBMS6821/ADBMS6822 transceivers create a bidirectional

isoSPI over a single twisted pair of wires, with increased safety

and noise immunity compared to a nonisolated interface. Using

capacitors or transformers, the transceiver translates standard SPI

signals (CS, SCK, PICO, and POCI) into pulses that can be sent

back and forth on twisted pair cables.

A typical battery management system (BMS) uses a transceiver

device that acts as a bridge between the microcontroller SPI port

and the isoSPI BMS monitors. The IP and IM transmitter/receiver

pins on the transceiver are connected across an isolation barrier to

the first BMS monitor in a daisy chain.

A typical non-BMS system uses two transceivers. The first is

paired with a microcontroller or other SPI controller. Its IP and IM

transmitter/receiver pins are connected across an isolation barrier

to a second transceiver that reproduces the SPI signals for use by

one or more peripheral devices.

The transmitter is a current-regulated differential driver. The voltage

amplitude is determined by the drive current and the equivalent

resistive load (cable characteristic impedance and termination re-

sistor, RM).

The receiver consists of a window comparator with a differential

voltage threshold of VRx. When VIP − V IM is greater than VRx, the

comparator detects a Logic 1. When VIP − VIM is less than −VRx (in

mV), the comparator detects a Logic −1. A Logic 0 (null) indicates

VIP − VIM is between the positive and negative thresholds.

The comparator outputs are sent to pulse timers (filters) that dis-

criminate between short and long pulses.

The ADBMS6822 (dual isoSPI transceiver) consists of two identical,

independent isoSPI transceivers. The ADBMS6822 functions as the

SPI to isoSPI bridge for both ends of a reversible isoSPI-capable

system.

ISOSPI PULSE DETAIL

The isoSPI transmitter can generate three voltage levels: +VA, 0

V, and −VA. To eliminate the DC signal component and enhance

reliability, isoSPI pulses are defined as symmetric pulse pairs. A +1

pulse pair is defined as a +VA pulse followed by a −VA pulse. A −1

pulse pair is −VA followed by +VA.

The duration of each pulse is defined as t1/2PW. The total isoSPI

pulse duration is 2 × t1/2PW. The transceiver allows two different

t1/2PW values so that four types of pulses can be transmitted, as

shown in Table 17.

Table 17. isoSPI Pulse Types

Pulse Type

First Level

Second Level

Ending Level

Long +1

+VA (150 ns)

−VA (150 ns)

0 V

Long −1

−VA (150 ns)

+VA (150 ns)

0 V

Short +1

+VA (50 ns)

−VA (50 ns)

0 V

Short −1

−VA (50 ns)

+VA (50 ns)

0 V

Long pulses are used to transmit CS changes. Short pulses trans-

mit data (PICO or POCI). The transceiver detects four types of

communication events from the SPI Controller: CS falling, CS

rising, SCK latching PICO = 0, and SCK latching PICO = 1. The

transceiver converts each event into one of the four pulse types, as

shown in Table 18.

Table 18. Controller Communication Events

SPI Controller Event

Transmitted Pulse

CS Rising

Long +1

CS Falling

Long −1

SCK Latching Edge, PICO = 1

Short +1

SCK Latching Edge, PICO = 0

Short −1

On the other side of the isolation barrier (that is, the other end

of the cable), another transceiver is configured to interface with

a SPI peripheral. This transceiver receives the transmitted pulses

and reconstructs the SPI signals on its output port, as shown in

Table 19. In addition, the peripheral device can transmit a return

data pulse to the controller to set the state of POCI. For additional

information, see the isoSPI Interaction and Timing section.

Table 19. Peripheral SPI Port Output

Received Pulse

SPI Port Action

Return Pulse

Long +1

Drive CS high

None

Long −1

Drive CS low

Short −1 pulse if POCI

= 0 (no return pulse if

POCI = 1)

Short +1

Set PICO = 1, pulse SCK

Short −1

Set PICO = 0, pulse SCK

A peripheral transceiver never transmits long CS pulses in regular

communication. However, it does transmit a long CS +1 pulse when

woken up by taking its WAKE pin high. For additional information,

see the WAKE Pin section. Furthermore, a peripheral only transmits

a short −1 pulse (when POCI = 0), never a short +1 pulse, which

allows multiple peripheral devices on a single cable without risk of

collisions (for additional information, see the Multidrop section).

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