Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

13 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

®

VD = V50 = 50V, V12 = 12V, VG = ‒2.5V, VBT50 = 55.2V, VSCL = VSDA = VENCAL = VENG = VENTX = VSCL50 = VSDA50 = VNTC = 5V, VREFIN =

0V, TA = ‒40 to +125 °C, unless otherwise specified

Parameter

Conditions

Min

Typ

Max

Units

I2C Master for ACT43850 and external I2C memory

fSCL50

SCL50 Output Clock

Frequency

0x17h [3:2] = 00

100

kHz

0x17h [3:2] = 01

200

kHz

0x17h [3:2] = 10

333

kHz

0x17h [3:2] = 11

1000

kHz

tLOW(SCL50)

SCL50 Pulse Width, Low

50% x

(1/fSCL50)

µs

tHIGH(SCL50)

SCL50 Pulse Width, High

50% x

(1/fSCL50)

µs

tSU(SDA)

SDA50 Set-up Time

25% x

(1/fSCL50)

ns

tH(SDA)

SDA50 Hold Time

25% x

(1/fSCL50)

ns

tSU(START50)

I2C START Set-up Time

50% x

(1/fSCL50)

ns

tSU(STOP50)

I2C STOP Set-up Time

50% x

(1/fSCL50)

ns

IDRAIN Calibrator

NAUTOCal

Delta-calibration Automatic

Re-Calibration Cycles

100

cycle

DSW50 Gate Drivers

tDEAD

Deadtime range (note 1)

-30

100

ns

tR(HSGU)

HSGU Turn ON Time

10% to 90%, no gate resistor

CGATE(FET) = 1.3nF

15

ns

tF(HSGD)

HSGD Turn OFF Time

90% to 10%, no gate resistor,

CGATE(FET) = 1.3nF

8

ns

tR(LSGU)

LSGU Turn ON Time

10% to 90%, no gate resistor

CGATE(FET) = 1.3nF

15

ns

tF(LSGD)

LSGD Turn Off Time

90% to 10%, no gate resistor,

CGATE(FET) = 1.3nF

8

ns

tD(CAL-TX)

Wait Time before ENTX Ready

(Internal calibration comp) to ENTX ready

10

ms

tD(HSGU)

HSGU Propagation Delay

ENTX

↑ to HSGU = H

100

ns

tD(LSGU)

LSGU Propagation Delay

ENTX

↓ to LSGU = L

100

ns

tD(PG, Rise)

PG Propagation Delay

From internal PG detection to VPG up

5

µs

tD(PG, Fall)

PG Propagation Delay

From internal PG detection to VPG down

0.2

µs