ACT43750 datasheet(10/43 Pages) QORVO

10 / 43 page

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

10 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

Parameter

Conditions

Min

Typ

Max

Units

VT+(GREF,chg)

GREF Io(GREF) Fast-Charge

Upper Threshold

((Internal reference)

– V

GREF) threshold to use

Io(GREF) fast-charging.

And hysteresis points to exit.

See Reference Voltage Noise Reduction.

> +35

VT+(GREF, hys)

GREF Io(GREF) Fast-Charge

Upper Hysteresis

<+20

VT-(GREF, chg)

GREF Io(GREF) Fast-Charge

Lower Threshold

<-35

VT-(GREF, hys)

GREF Io(GREF) Fast-Charge

Lower Hysteresis

>-20

Ro(GREF, chg)

GREF Io(GREF) Fast-Charge

Output Resistance

During Io(GREF) fast-charging

480

Ω

Ro(GREF)

GREF Output Resistance

0xEh [3:2] = 00

0.5

Ω

0xEh [3:2] = 01

4.5

Ω

0xEh [3:2] = 10

Ω

0xEh [3:2] = 11

250

Ω

IO(GREF)

GREF Pre-Charge Current

0xEh [1:0] = 00

µA

0xEh [1:0] = 01

µA

0xEh [1:0] = 10

100

µA

0xEh [1:0] = 11

200

µA

VLSR

LSR Voltage Reference

All 0x0Fh [3:0] options

-5%

+5%

I2C Slave for MCUs/Controllers

VIT+(SCL),VIT+(SDA)

SCL, SDA Input Threshold

Falling edge for HLOGIC

0.55

VIT-(SCL),VIT-(SDA)

Rising edge for HLOGIC

1.25

ILKG(SDA)

SDA Leakage Current

VSDA = 5V

µA

VOL(SDA)

SDA Output Voltage

5mA Current into SDA pin

0.35

CI(SCL), CI(SDA)

SCL, SDA Terminal

Capacitance

I2C Master for ACT43850 and External Memory

VIT+(SDA50)

SDA50 Input Threshold

Falling edge for HLOGIC

0.55

VIT-(SDA50)

Rising edge for HLOGIC

1.25

ILKG(SCL50)

ILKG(SDA50)

SCL50, SDA50 Leakage

Current

VSCL50 = VSDA50 = 5 V

µA

VOL(SCL50)

VOL(SDA50)

SCL50, SDA50 Output Voltage

5mA Current into SDA50 and SCL50 pins

0.35

CI(SCL50), CI(SDA50)

SCL50, SDA50 Terminal

Capacitance

RPU(SDA50),RPU(SCL50)

SDA50, SCL50 Pull-up

Resistance

Internal pull-up

3.3

Ω

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