SML2108F datasheet(15/21 Pages) SUMMIT

15 / 21 page

2053 2.2 11/07/00

SML2108

SUMMIT MICROELECTRONICS, Inc.

PRELIMINARY

In the write mode the SML2108 receives eight bits of data,

then generates an Acknowledge signal. It will continue to

generate ACKs until a Stop condition is generated by the

Master. See Figure 13.

Random Address Read

Random address Read operations allow the Master to

access any memory location in a random fashion. This

operation involves a two-step process. First, the master

issues a write command which includes the start condition

and the Slave address field (with the R/W bit set to Write)

followed by the address of the word it is to read. This

procedure sets the internal address counter of the

SML2108 to the desired address. After the word address

acknowledge is received by the Master, it immediately

reissues a start condition followed by another Slave ad-

dress field with the R/W bit set to Read. The SML2108 will

respond with an Acknowledge and then transmit the 8 data

bits stored at the addressed location. At this point, the

Master does not acknowledge the transmission, but does

generate a Stop condition. The SML2108 discontinues

data transmission.

Figure 12. Read

Figure 13. Write

Sequential READ

Sequential Reads can be initiated as either a current

address Read or a random access Read. The first word

is transmitted as with the other byte read modes (current

address byte Read or random address byte Read). How-

ever, the Master now responds with an Acknowledge,

indicating that it requires additional data. The SML2108

continues to output data for each Acknowledge received.

The Master terminates the sequential Read operation by

not responding with an Acknowledge, and issues a Stop

condition. During a sequential read operation the internal

address counter is automatically incremented with each

Acknowledge signal. For Read operations all address bits

are incremented, allowing the entire array to be read using

a single Read command. After a count of the last memory

address the address counter will ‘roll-over’ and the

memory will continue to output data.

The protocol for reading and writing to the registers and

the lookup table are illustrated in Figures 14 through 24.

Master

SDA

Slave

1 0

xx x W

xx x xx x xx

2053 Fig13

Master

SDA

Slave

1 0

xx x R

x x xx x xx

Optional

2053 Fig12

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