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TMP86FS23UG датащи(PDF) 74 Page - Toshiba Semiconductor |
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TMP86FS23UG датащи(HTML) 74 Page - Toshiba Semiconductor |
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74 / 252 page ![]() Page 62 5. I/O Ports 5.6 Port P7 (P77 to P70) TMP86FS23UG 5.6 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P7 is also used as a segment output of LCD. Input/output mode is specified by the P7 control register (P7CR). When used as an input port, the corresponding bit of P7CR and P7LCR should be cleared to “0”. When used as an output port, the corresponding bit of P7CR should be set to “1”, and the respective P7LCR bit should be cleared to “0”. When used as a segment pins of LCD, the respective bit of P7LCR should be set to “1”. During reset, the output latch (P7DR), P7CR and P7LCR are initialized to “0”. When the bit of P7CR and P7LCR is “0”, the corresponding bit data by read instruction is a terminal input data. When the bit of P7CR is “0” and that of P7LCR is “1”, the corresponding bit data by read instruction is always “0“. When the bit of P7CR is “1”, the corresponding bit data by read instruction is the value of P7DR. Note: Asterisk (*) indicates “1” or “0” either of which can be selected. Figure 5-7 Port P7 Table 5-9 Register Programming for Multi-function Ports Function Programmed Value P7DR P7CR P7LCR Port input * “0” “0” Port “0” output “0” “1” “0” Port “1” output “1” “1” “0” LCD segment output * * “1” Table 5-10 Values Read from P7DR and Register Programming Conditions Values Read from P7DR P7CR P7LCR “0” “0” Terminal input data “0” “1” “0” “1” “0” Output latch contents “1” P7LCRi Output latch Data output (P7DRi) LCD data output STOP OUTEN P7LCRi input P7CRi P7CRi input Data input (P7DRi) P7i Note:i=7 to 0 D Q D Q D Q |
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