TMP86CS44UG datasheet(133/172 Pages) TOSHIBA

133 / 172 page

Page 123

TMP86CS44UG

Figure 11-15 Example of Transmit/Receive (Transmit) Error Processing

(b) Receive errors

Receive errors occur on the following situation. To protect SIORDB and the shift register

contents, the received data is ignored while the SIOSR<RXERR> is “1”.

• Shift operation is finished before reading out received data from SIORDB at

SIOSR<RXF> is “1” in an external clock operation.

If receive error occurs, set the SIOCR1<SIOS> to “0” for reading the data that received

immediately before error occurence. And read the data from SIORDB. Data in shift reg-

ister (at errors occur) can be read by reading the SIORDB again.

When SIOSR<RXERR> is cleared to “0” after reading the received data, SIOSR<RXF>

is cleared to “0”.

After clearing SIOCR1<SIOS> to “0”, when 8-bit serial clock is input to SCK pin, re-

ceive operation is stopped. To restart the receive operation, confirm that SIOSR<SIOF>

is cleared to “0”.

If the received error occurs, set the SIOCR1<SIOINH> to “1” for stopping the receive

operation immediately. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register

and SIOTDB register are initialized.

Writing transmit

data B

Writing transmit

data A

Unknown

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0

Start shift

operation

Start shift

operation

Start shift

operation

Reading received

data F

Reading received

data E

Reading received

data D

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

SCK

pin output

SO pin

SI pin

INTSIO

interrupt

request

SIOSR<TXF>

SIOSR<RXF>

SIORDB

SIOTDB

SIOSR<TXERR>

SIOCR1<SIOINH>

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