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TMP86FS64FG датащи(PDF) 49 Page - Toshiba Semiconductor

номер детали TMP86FS64FG
подробное описание детали  8 Bit Microcontroller
PDF  252 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86FS64FG датащи(HTML) 49 Page - Toshiba Semiconductor

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Page 37
TMP86FS64FG
Figure 2-15 Reset Circuit
2.3.2 Address-Trap-Reset
If the CPU runs away due to spurious noises and attempts to fetch an instruction form the on-chip RAM
(WDTCR1<ATA> = 1) or the SFR area, an address-trap-reset is generated. The reset time is a maximum of 24/
fc [s] (1.5
µs @16.0 MHz).
If the CPU runs away due to spurious noises and attempts to fetch an instruction from the on-chip RAM
(WDTCR1<ATAS> = 1), the DBR or the SFR area, an address-trap-reset is generated. The reset time is a max-
imum of 24/fc [s] (1.5
µs @16.0 MHz).
Note:Either a reset or an interrupt can be selected for an address-trap. An address-trap area can be specified.
Note 1: "a" is the address in on-chip RAM (WDTCR1<ATAS>=1), SFR or DBR area.
Note 2: During the reset release process, the reset vector "r" is read out, and an instruction at the address "r" is fetched and
decoded.
Figure 2-16 Address Trap Reset
2.3.3 Watchdog Timer Reset
Refer to "Watchdog Timer".
2.3.4 System Clock Reset
Either one of the following conditions is met, a system clock reset is generated automatically to prevent the
CPU to be in the deadlock condition. (Oscillation is continued.)
• SYSCR2<XEN> and SYSCR2<XTEN> are cleared to 0.
• SYSCR2<XEN> is cleared to 0 when SYSCR2<SYSCK> = 0.
• SYSCR2<XTEN> is cleared to 0 when SYSCR2<SYSCK> = 1.
The reset time is a maximum of 24/fc [s] (1.5
µs @160.0 MHz).
Reset input
VDD
RESET
Internal factor reset
output circuit
Watchdog timer
Address trap detection
System clock detection
Instruction
execution
Internal reset signal
An address-trap is generated
JP
a
4/fc to 12/fc [s]
max 24/fc [s]
16/fc [s]
Reset released
Instruction at r
address



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