TMP86FS64FG datasheet(48/252 Pages) TOSHIBA

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Page 36

2. Operational Descriptions

2.3 Reset Circuit

TMP86FS64FG

2.3 Reset Circuit

TMP86FS64FG has four types of reset, that are an external reset, address trap reset, watchdog timer reset and sys-

tem clock reset.

An address trap reset, watchdog timer reset and system clock reset are internal factor resets. When detecting these

reset requests, TMP86FS64FG is in the reset state during a maximum of 24/fc [s].

(During a flash reset, the RESET pin is held high.)

Since the internal factor reset circuits that are watchdog timer reset, address trap reset and system clock reset are

not initialized upon power-up, a maximum reset time may become 24/fc [s] (1.5

µs @ 16.0 MHz).

Table 2-6 shows the on-chip hardware initialization by reset operation.

2.3.1 External Reset Input

The RESET pin is the hysteresis input with pull-up resistance. When the RESET pin is held low for a mini-

mum of 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and sta-

ble oscillation, a reset is triggered and internal state is initialized.

When the RESET pin input goes high, the reset operation is released , and program execution starts at the

vector address stored at addresses FFFE to FFFH.

Table 2-6 On-Chip Hardware Initialization by Reset Operation

On-Chip Hardware

Initial Value

On-Chip Hardware

Initial Value

Program counter (PC)

(FFFEH)

Prescaler and divider of the timing generator

Stack pointer (SP)

Not initialized

General-purpose register

(W, A, B, C, D, E, H, L, IX, IY)

Not initialized

Jump status flag (JF)

Not initialized

Watchdog timer

Enabled

Zero flag (ZF)

Not initialized

Output latch of I/O port

Refer to description of

each I/O port

Carry flag (CF)

Not initialized

Half carry flag (HF)

Not initialized

Sign flag (SF)

Not initialized

Overflow flag (VF)

Not initialized

Interrupt master enable flag (IMF)

Interrupt individual enable flag (EF)

Control register

Refer to description of

each register

Interrupt latch (IL)

RAM

Not initialized

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