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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86FS64FG датащи(PDF) 39 Page - Toshiba Semiconductor |
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TMP86FS64FG датащи(HTML) 39 Page - Toshiba Semiconductor |
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39 / 252 page  Page 27 TMP86FS64FG 2.2.4.2 IDLE1/2 and SLEEP1/2 Modes The IDLE1/2 and SLEEP1/2 modes controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is held during the IDLE1/2 or SLEEP1/2 mode. 1. The CPU and watchdog timer are halted. On-chip peripherals continue operation. 2. The data memory, registers, program status words, port output latches hold the status that acti- vated the IDLE1/2 or SLEEP1/2 mode. 3. The program counter holds the address of the instruction after next to the instruction to activate IDLE1/2 or SLEEP1/2 mode. Figure 2-10 IDLE1/2 and SLEEP1/2 Modes CPU and WDT halted Interrupt processing Reset Yes No No No No IMF = "1" Reset input Yes Yes (Interrupt service routine) (Normal execution) Interrupt request Entering the IDLE1/2 or SLEEP1/2 mode (Instruction) Execution of the instruction immediately following the instruction that activated the IDLE1/2 or SLEEP1/2 mode |
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