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DSPI-FIFO датащи(PDF) 5 Page - Digital Core Design |
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DSPI-FIFO датащи(HTML) 5 Page - Digital Core Design |
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5 / 6 page ![]() All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. DSPI_FIFO allows direct interface to almost any existing synchronous serial peripheral. SPI Controller manages the Master/Slave operation and controls the transmission. The SPI Controller manages the transmission speed and format (Phase and polarity). Con- troller is also responsible for generating of interrupt request and detection of transmission errors. PERFORMANCE The following table gives a survey about the Core performance in the ALTERA® de- vices after Place & Route (all key features have been included): Device Speed grade Logic Cells Fmax CYCLONE -6 324 171 MHz CYCLONE2 -6 314 197 MHz STRATIX -5 324 206 MHz STRATIX2 -3 273 313 MHz STRATIXGX -5 324 210 MHz APEX2A -7 370 178 MHz APEX20KC -7 369 152 MHz APEX20KE -1 369 115 MHz APEX20K -1 369 94 MHz ACEX1K -1 369 103 MHz FLEX10KE -1 369 103 MHz Core performance in ALTERA® devices Transfer Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI_FIFO allows direct interface to almost any existing synchronous serial peripheral. 6 6 5 5 4 4 3 3 2 21 1LSB MSB MSB LSB 1 2 3 45 67 8 SC K CYC LE# SC K (C PO L =0) SC K (C PO L=1) MO SI MISO SS 6 6 5 5 4 4 3 3 2 21 1LSB MSB MSB LSB 1 2 3 45 67 8 SC K CY CLE # SC K (C P O L =0) SC K (C P O L =1) MO SI MISO SS |
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