All trademarks mentioned in this document

http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

LICENSI N G

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

○

VHDL, Verilog source code called HDL

Source

○

Encrypted, or plain text EDIF called Netlist

○

Encrypted Netlist only

○

HDL Source

○

Netlist

○

HDL Source to Netlist

○

Single Design to Unlimited Designs

SYMBO L

datai(7:0)

addr(7:0)

scki

mi

si

ss

clk

rst

datao(7:0)

cs

rd

we

ss7o

ss6o

ss5o

ss4o

ss3o

ss2o

ss1o

ss0o

scko

scken

mo

so

soen

irq

rxrdy

txrdy

PINS DESCRIPTION

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

datai(7:0)

input

Data bus input

addr(1:0)

input

Processor address lines

cs

input

Chip select

rd

input

Processor read strobe

we

input

Processor write strobe

scki

input

SPI clock input

mi

input

Master serial data input

si

input

Slave serial data input

ss

input

Slave select

datao(7:0)

output

Data bus output

irq

output

Interrupt request

txrdy

output

Transmitter ready output

rxrdy

output

Receiver ready output

scko

output

SPI clock output

scken

output

SPI clock output enable

mo

output

Master serial data output

so

output

Slave serial data output

soen

output

Slave output enable

ss7o-ss0o

output

Slave select outputs